Abstract: A method can include receiving a request to read data from a block of a memory device coupled with a processing device, determining, using a data structure mapping block identifiers to corresponding voltage distribution parameter values, a voltage distribution parameter value associated with the block of the memory device, determining a set of read levels associated with the voltage distribution parameter value, wherein each read level in the set of read levels corresponds to a respective voltage distribution of at least one memory cell comprised by the block, and reading, using the determined set of read levels, data from the block of the memory device.

Abstract: A neural network system includes an array circuit and a gate circuit. The array circuit generates output data based on first input data, by a plurality of memory cells. The gate circuit outputs a select signal, based on defect information which is obtained based on the output data. A target memory cell, which is activated in response to the select signal, from among the plurality of memory cells is trained based on second input data, and the defect information is associated with a defect included in the plurality of memory cells.

Abstract: When programming and verifying a memory device which includes a plurality of memory cells and a plurality of word lines, a first coarse programming is first performed on a first memory cell among the plurality of memory cells which is controlled by a first word line among the plurality of word lines, and then a second coarse programming is performed on a second memory cell among the plurality of memory cells which is controlled by a second word line among the plurality of word lines. Next, a first coarse verify current is used for determining whether the first memory cell passes a coarse verification and a second coarse verify current is used for determining whether the second memory cell passes a second coarse verification, wherein the second coarse verify current is smaller than the first coarse verify current.

Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including identifying an amount of storage charge loss (SCL) that has occurred on an open block of the memory device, the open block having one or more erased pages, determining that the amount of SCL satisfies a threshold criterion corresponding to an acceptable amount of SCL to occur on the open block, and responsive to determining that the amount of SCL satisfies the threshold criterion, keeping the open block open for programming the one or more erased pages.

Abstract: A semiconductor storage device includes a memory cell connected to a word line, and a control circuit configured to execute a write operation that repeats a program loop including a program operation of applying a program voltage to the word line and a verification operation to be executed after the program operation. The control circuit, during the write operation, increases the program voltage by a first amount each time the program loop is repeated, and after the write operation is interrupted and resumed, changes the increase in the program voltage from the first amount to a second amount, which is a positive number smaller than the first amount.

Abstract: A sense amplifier includes a sense amplifying unit, first and second isolation units, and first and second offset cancellation unit. The sense amplifying unit includes a first P-type metal-oxide-semiconductor (PMOS) transistor, a second PMOS transistor, a first N-type metal-oxide-semiconductor (NMOS) transistor, and a second NMOS transistor. In a layout of the sense amplifier, the first and second PMOS transistors are disposed in a central region of the sense amplifier, the first and second NMOS transistors are disposed at opposite sides of the sense amplifier from each other, the first isolation unit and the first offset cancellation unit are disposed between the first PMOS transistor and the first NMOS transistor, and the second isolation unit and the second offset cancellation unit are disposed between the second PMOS transistor and the second NMOS transistor. In other layouts, the locations of the PMOS transistors and NMOS transistors may be reversed.

Abstract: A method can include receiving a request to read data from a memory cell of a memory device coupled with the processing device, determining a voltage distribution parameter value associated with the memory cell, determining a set of read levels associated with the voltage distribution parameter value, wherein each read level in the determined set of read levels corresponds to a respective voltage distribution of the memory cell, and reading, using the determined set of read levels, data from the memory cell. The voltage distribution parameter value can be determined by identifying a particular voltage distribution of the memory cell by sampling the memory cell at a plurality of voltage levels, and determining the voltage distribution parameter value based on the particular voltage distribution. The voltage distribution parameter value can be a voltage value that is included in the particular voltage distribution.

Abstract: A device may include a first die having a first circuit and a second die having a second circuit. The die may be separated by a material layer. The material layer may include multiple through-silicon vias (TSVs) for electrically coupling the first die to the second die. A first TSV of the TSVs may electrically couple the first circuit to the second circuit and a second TSV of the TSVs may include a redundant TSV that electrically bypasses the first TSV to couple the first circuit to the second circuit if a fault is detected in the first TSV.

Abstract: A semiconductor storage device includes a memory transistor and a word line connected to a gate electrode of the memory transistor. When a write sequence is interrupted before a k+1th verification operation is ended after a kth verification operation is ended in the nth write loop of the write sequence, a voltage equal to or higher than a verification voltage corresponding to a first verification operation in the nth write loop is supplied to the word line before start of the k+1th verification operation after resumption of the write sequence. A time from the resumption of the write sequence to the start of the k+1th verification operation is shorter than a time from start of the first verification operation to end of the kth verification operation in the nth write loop.

Abstract: An amount of threshold voltage distribution shift is determined. The threshold voltage distribution shift corresponds to an amount of time after programming of a reference page of a block of a memory device. A program-verify voltage is adjusted based on the amount of threshold voltage distribution shift to obtain an adjusted program-verify voltage. Using the adjusted program-verify voltage, a temporally subsequent page of the block is programmed at a time corresponding to the amount of time after the programming of the reference page.

Abstract: Various embodiments provide for erasing of one or more partially-programmed memory units of a memory device. In particular, various embodiments provide for monitoring (e.g., tracking) of partial program/erase cycles for a memory unit (e.g., block) of a memory device, and performing an erasure of the memory unit based on the monitoring.

Abstract: Technology for two-sided adjacent memory cell interference mitigation in a non-volatile storage system is disclosed. During reading of target memory cells, the storage system applies a suitable magnitude read pass voltage to a first unselected word line adjacent to a target word line to compensate for interference from adjacent cells on the first unselected word line while applying a suitable magnitude read reference voltage to the target word line to compensate for interference from adjacent cells on a second unselected word line on the other side of the target word line. The read pass voltage may compensate for interference due to charge being added to when programming cells on the first unselected word line after programming the target cells. The read reference voltage may compensate for interference due to charge movement near the target cells that results from charge stored in the cells on the second unselected word line.

Abstract: According to one embodiment, an information processing apparatus includes a connector into which a first-type semiconductor storage device operating with n types of power supply voltages or a second-type semiconductor storage device operating with m types of power supply voltages less than the n types of power supply voltages is capable of being placed. The apparatus checks whether or not a notch is formed at a predetermined position of a semiconductor storage device placed into the connector, and supplies the m types of power supply voltages to the semiconductor storage device when the notch is formed at the predetermined position.

Abstract: A semiconductor memory includes a first memory cell configured to be set with a first threshold voltage, the first threshold voltage being one of different threshold voltage levels, a second memory cell configured to be set with a second threshold voltage, the second threshold voltage being one of different threshold voltage levels, a first word line coupled to the first memory cell, a second word line coupled to the second memory cell, and a controller configured to read data of one of different bits based on a combination of the first threshold voltage of the first memory cell and the second threshold voltage of the second memory cell.

Abstract: A nonvolatile memory device includes a peripheral circuit region and a memory cell region vertically connected with the peripheral circuit region, the peripheral circuit region including at least one first metal pad, and the memory cell region including at least one second metal pad directly connected with the at least one first metal pad. A method of programming the nonvolatile memory device includes: receiving a programming command, data for a plurality of pages, and an address corresponding to a selected word-line; programming the data for one of the pages to an unselected word-line; reading data of a previously programmed page from the selected word-line; and programming the data for the remaining pages and the data of the previously programmed page to the selected word-line.

Abstract: Disclosed herein is an apparatus that includes: a first diffusion region having a rectangular shape and including first and second source/drain regions arranged in the first direction; a second diffusion region having a rectangular shape and including third to fifth source/drain regions arranged in the first direction; a first gate electrode extending in a second direction, and provided between the first and second source/drain regions and between the third and fourth source/drain regions; and a second gate electrode extending in the second direction, and provided between the fourth and fifth source/drain regions. The first and third source/drain regions are brought into the same potential as each other, and the second and fourth source/drain regions are brought into the same potential as each other.

Abstract: An apparatus includes a plurality of solid-state storage elements, a plurality of control lines coupled to the plurality of solid-state storage elements, and control circuitry in communication with the plurality of control lines. The control circuitry is configured to during a first phase of a control line pre-charging stage, charge one or more unselected control lines of the plurality of control lines using a regulated charging current for a period of time based at least in part on a predicted parasitic capacitance associated with the programming state of the control lines, and during a second phase of the control line pre-charging stage, charge the one or more unselected bit lines to an inhibit voltage level using an unregulated charging current.

Abstract: A method of programming a nonvolatile memory device includes: receiving a programming command, data for a plurality of pages, and an address corresponding to a selected word-line; programming the data for one of the pages to an unselected word-line; reading data of a previously programmed page from the selected word-line; and programming the data for the remaining pages and the data of the previously programmed page to the selected word-line.

Abstract: Technology for sensing non-volatile memory cells in which one or more sense nodes are charged to a sense voltage having a magnitude that improves sensing accuracy. One sense node may be charged to different sense voltages when sensing different memory cells at different times. Multiple sense nodes may be charged to a corresponding multiple different sense voltages when sensing different memory cells at the same time. The one or more sense nodes are allowed to discharge based on respective currents of memory cells for a pre-determined time while applying a reference voltage to the memory cells. The Vts of the selected memory cells are assessed based on respective voltages on the one or more of sense nodes after the pre-determined time. Different sensing voltages may be used based on bit line voltage, bit line resistance, distance of memory cells from the sense node, or other factors.

Abstract: A nonvolatile memory device includes multi-level cells in a memory cell array including a plurality of memory blocks, and each of the memory blocks includes a plurality of pages. A method of operating the nonvolatile memory device includes pre-programming multi-bit data in a pre-program block of the memory blocks, dividing the multi-level cells into a plurality of state groups based on state codes indicating states of the multi-level cells to generate digest data indicating state group codes corresponding to the state groups, and programming the digest data in a digest block of the memory blocks.