Abstract: According to one embodiment, a magnetic storage device includes a nonvolatile magnetic memory including a magnetoresistance effect element capable of storing data. A magnetic sensor is configured to measure the magnitude of an external magnetic field. A controller is configured to detect errors in the data at first time intervals when the measured magnitude of the external magnetic field is less than a threshold value and to detect errors in the data at second time intervals shorter than the first time interval when the measured magnitude of the external magnetic field is equal to or greater than the threshold value.

Abstract: A semiconductor memory device includes a memory block including a plurality of memory cells programmed to a plurality of program states during a program operation, a voltage generator to generate and apply a program voltage and a select line voltage to the memory block during the program operation, and a read and write circuit to temporarily store program data during the program operation and control a potential of bit lines of the memory block based on the temporarily stored program data. The voltage generator generates the select line voltage as a first select line voltage during a first program operation on some program states among the plurality of program states, or as a second select line voltage for which a potential is lower than a potential of the first select line voltage during a second program operation on remaining program states among the plurality of program states.

Abstract: A semiconductor circuit and an operating method for the same are provided. The method includes the following steps. A memory circuit is operated during a first timing to obtain a first memory state signal S1. The memory circuit is operated during a second timing after the first timing to obtain a second memory state signal S2. A difference between the first memory state signal S1 and the second memory state signal S2 is calculated to obtain a state difference signal SD. A calculating is performed to obtain an un-compensated output data signal OD relative with an input data signal ID and the second memory state signal S2. The state difference signal SD and the un-compensated output data signal OD are calculated to obtain a compensated output data signal OD?.

Abstract: A non-volatile memory includes a cell array, a current supply circuit, a path selecting circuit, a verification circuit and a control circuit. During a sample period of a verification action, the control circuit controls the current supply circuit to provide n M-th reference currents to the verification circuit and convert the n M-th reference currents into n reference voltages. During a verification period of the verification action, the control circuit controls n multi-level memory cells of a selected row of the cell array to generate n cell currents to the verification circuit and convert the n cell currents into n sensed voltages. The n verification devices generate the n verification signals according to the reference voltages and the sensed voltages. Accordingly, the control circuit judges whether the n multi-level memory cells have reached an M-th storage state.

Abstract: A semiconductor apparatus may include a repair circuit configured to activate a redundant line of a cell array region by comparing repair information and address information. The semiconductor apparatus may include a main decoder configured to perform a normal access to the cell array region by decoding the address information. The address information may include both column information and row information.

Abstract: A system includes a memory device including a plurality of groups of memory cells and a processing device that is operatively coupled to the memory device. The processing device is to receive a request to determine a reliability of the plurality of groups of memory cells. The processing device is further to perform, in response to receipt of the request, a scan operation on a sample portion of the plurality of groups of memory cells to determine a reliability of the sample portion that is representative of the reliability of the plurality of groups of memory cells.

Abstract: An integrated circuit includes a primary memory array with cells switchable between first and second states. The circuit also includes sacrificial memory cells; each fabricated to be switchable between the first and second states and associated with at least one row of the primary array. A controller is configured to detect a write operation to a row of the primary array, stress a sacrificial cell associated with the row and detect a failure of the associated sacrificial cell. The sacrificial cells are fabricated to have lower write-cycle endurance than cells of the primary array or are subjected to more stress. Failure of a row of the primary array is predicted based, at least in part, on a detected failure of the associated sacrificial cell.

Abstract: Memories might include a plurality of strings of memory cells, a plurality of access lines each connected to the strings of memory cells, and a controller configured to cause the memory to determine a particular voltage level applied to each of the access lines that is deemed to activate each memory cell of a first subset of the strings of series-connected memory cells programmed to store respective data states that are each lower than or equal to a first data state of a plurality of data states, apply the particular voltage level to a particular access line of the plurality of access lines, and for each memory cell connected to the particular access line that is contained in a second subset of the strings of series-connected memory cells, determine whether that memory cell is deemed to be activated while applying the particular voltage level to the particular access line.

Abstract: A semiconductor storage device includes memory cells, select transistors, memory strings, first and second blocks, word lines, and select gate lines. In the memory string, the current paths of plural memory cells are connected in series. When data are written in a first block, after a select gate line connected to the gate of a select transistor of one of the memory strings in the first block is selected, the data are sequentially written in the memory cells in the memory string connected to the selected select gate line. When data are written in the second block, after a word line connected to the control gates of memory cells of different memory strings in the second block is selected, the data are sequentially written in the memory cells of the different memory strings in the second block which have their control gates connected to the selected word line.

Abstract: Methods, systems, and devices supporting configurable resistivities for lines in a memory device, such as access lines in a memory array are described. For example, metal lines at different levels of a memory device may be oxidized to different extents in order for the lines at different levels of the memory device to have different resistivities. This may allow the resistivity of lines to be tuned on a level-by-level basis without altering the fabrication techniques and related parameters used to initially form the lines at the different levels, which may have benefits related to at least reduced cost and complexity. Lines may be oxidized to a controlled extent using either a dry or wet process.

Abstract: The present disclosure relates to a memory device that includes a plurality of memory cells. The memory device also includes a peripheral circuit configured to perform a program operation of storing data in the plurality of memory cells, which includes a plurality of program loops each including an operation of applying a program voltage to a selected word line commonly connected to the plurality of memory cells and a verify operation of applying at least one verify voltage among verify voltages respectively corresponding to target program states of the plurality of memory cells. The memory device additionally includes control logic configured to control the peripheral circuit so that the at least one verify voltage increases according to a program loop of the plurality of program loops during the program operation.

Abstract: The present technology relates to an electronic device. For example, the present technology relates to a memory device and a method of operating the memory device. A memory device according to an embodiment includes a memory cell, a page buffer, and a test performer configured to control the page buffer to sequentially apply a first test voltage and a second test voltage of a level lower than a level of the first test voltage to a sensing node of the page buffer through a bit line, and detect a defect of the sensing node according to whether a potential level of the sensing node is changed.

Abstract: Described herein are one access transistor and one ferroelectric capacitor (1T-1FE-CAP) memory cells in diagonal arrangements, as well as corresponding methods and devices. When access transistors of memory cells are implemented as FinFETs, then, in a first diagonal arrangement, memory cells are arranged so that the BLs for the cells are diagonal with respect to the fins of the access transistors of the cells, while the WLs for the cells are perpendicular to the fins. In a second diagonal arrangement, memory cells are arranged so that the fins of the access transistors of the cells are diagonal with respect to the WLs for the cells, while the BLs for the cells are perpendicular to the WLs. Such diagonal arrangements may advantageously allow achieving high layout densities of 1T-1FE-CAP memory cells and may benefit from the re-use of front-end transistor process technology with relatively minor adaptations.

Abstract: Apparatuses, systems, and methods for high-pass filtering pre-emphasis circuits. A device may use a pre-emphasis driver to provide a multi-level signal based on multiple binary signals. The pre-emphasis driver includes a primary driver coupled in parallel with at least one equalizer path, each of which includes an equalizer driver and a filtering element. The filtering element may be an AC filtering element, such as a capacitor. The equalizer paths may contribute equalized signal(s) which have a high-pass filtering behavior. The pre-emphasis circuit may combine the primary signal from the primary driver and the equalized signals to generate an overall output multi-level signal. In some embodiments, the pre-emphasis driver may be a pulse amplitude modulated (PAM) driver, such as a PAM4 driver with four levels of the multi-level driver.

Abstract: A non-volatile memory apparatus and method of operation are provided. The apparatus includes storage elements connected to a word line. Each of the storage elements is configured to be programmed to a respective target data state. The apparatus also includes a respective bit line associated with each of the storage elements and a control circuit configured to apply a plurality of program pulses to the word line that progressively increase by a program step voltage. The control circuit counts an over programming number of the storage elements having a threshold voltage exceeding an over programming verify level of the respective target data state that is less than a default verify level and based on the program step voltage. The control circuit adjusts a voltage of the respective bit line to one or more adjusted levels in response to the over programming number being greater than a predetermined over programming number.

Abstract: A controller that controls a nonvolatile memory apparatus may include a first memory configured to temporarily store user data, a second memory including a plurality of memory regions composed of one or more meta regions for storing meta data and at least one spare region, and a processor configured to control the first memory and the second memory and perform first start-gap wear leveling on at least one meta region using the at least one spare region as a gap.

Abstract: A semiconductor memory device includes a memory cell array, a peripheral circuit, a current sensing circuit, and control logic. The memory cell array includes a plurality of memory cells. The peripheral circuit performs a program operation on selected memory cells connected to a selected word line among the plurality of memory cells. The current sensing circuit generates a pass signal or a fail signal by performing a current sensing operation on the selected memory cells. The control logic receives the pass signal or the fail signal and controls an operation of the peripheral circuit and the current sensing circuit. The control logic controls the current sensing circuit and the peripheral circuit to perform the current sensing operation and an operation of applying a program pulse to the selected word line based on a program progress state of the selected memory cells.

Abstract: Provided herein is a semiconductor memory device and a method of operating the semiconductor memory device. The semiconductor memory device includes: a memory cell array comprising a plurality of memory cells to be programmed to a plurality of programmed states; a peripheral circuit configured to perform a program operation on selected memory cells among the plurality of memory cells; a current sensing circuit configured to perform an individual state current sensing operation and an overall state current sensing operation on selected memory cells among the memory cells and determine a result of the program operation on each for the plurality of programmed states; and control logic configured to control the peripheral circuit and the current sensing circuit such that an operation period of the overall state current sensing operation at least partially overlaps with an operation period of a bit line set-up operation of the program operation.

Abstract: Over time, the number of write cycles required to successfully program a multi-level cell (MLC) is reduced. Since a hard-coded value does not change over the lifetime of the device, the device may perform too many verify steps at one stage of the device lifetime and wait too long to begin verification at another stage of the device lifetime, reducing performance of the device. As discussed herein, verification for higher voltage level programming is delayed until verification for lower voltage level programming reaches at least a threshold level of success instead of using a hard-coded number of verify steps to skip. As a result, the performance drawbacks associated with skipping a hard-coded number of verify cycles may not occur.

Abstract: Systems and methods for reducing the size of sub-blocks within a physical memory block for a three-dimensional non-volatile memory using buried source lines are described. The physical memory block may be fabricated using dual buried source lines such that sub-blocks within the physical memory block may be individually selected in both a horizontal word line direction and a vertical NAND string direction. The physical memory block may include a plurality of sub-blocks that are individually selectable and that share bit lines and/or source-side select gate lines. The plurality of sub-blocks that are individually selectable may correspond with different portions of the same NAND string in which a first sub-block of the plurality of sub-blocks connects to a drain-side select gate for the NAND string and a second sub-block of the plurality of sub-blocks connects to a source-side select gate for the NAND string.