Abstract: An integrated circuit to drive a number of fluid actuation devices, comprising a circuit configured to have a memory access state which can be set to one of an enabled state and disabled state. The integrated circuit to include a fluid actuation circuit to transmit selection information for a fluid actuation device, the selection information comprising a data state bit. The integrated circuit to include a memory cell array, configured so that each memory cell is accessible by the memory access state being enabled, and the data state bit being set.

Abstract: A memory device includes receivers that use CMOS signaling levels (or other relatively large signal swing levels) on its command/address and data interfaces. The memory device also includes an asynchronous timing input that causes the reception of command and address information from the CMOS level receivers to be decoded and forwarded to the memory core (which is self-timed) without the need for a clock signal on the memory device's primary clock input. Thus, an activate row command can be received and initiated by the memory core before the memory device has finished exiting the low power state. Because the row operation is begun before the exit wait time has elapsed, the latency of one or more accesses (or other operations) following the exit from the low power state is reduced.

Abstract: A flash memory device includes a plurality of memory planes each contains arrays of memory cells; a host interface for accessing the plurality of memory planes by an external host; and a controller connected to the plurality of memory planes via a memory interface and controlling the host interface for accessing the plurality of memory planes. The controller is configured to perform: receiving one or more commands on the host interface from the external host; determining whether to perform asynchronous multi-plane independent (AMPI) read operation corresponding to the commands; and after determining to start the AMPI read operation, accessing the memory planes in parallel according to the commands, and completing the AMPI read operation using an order of the commands determined based on an indicator signal provided to the controller to correspond to a sequence of the commands received on the host interface.

Abstract: A method of generating a multi-level signal having one of three or more voltage levels that are different from each other, the method including: performing a first voltage setting operation in which first and second voltage intervals are adjusted to be different from each other, wherein the first voltage interval represents a difference between a first pair of adjacent voltage levels and the second voltage interval represents a difference between a second pair of adjacent voltage levels; performing a second voltage setting operation in which a voltage swing width is adjusted, the voltage swing width representing a difference between a lowest and a highest voltage level among the three or more voltage levels; and generating an output data signal that is the multi-level signal based on input data including two or more bits, a result of the first voltage setting operation and a result of the second voltage setting operation.

Abstract: A memory device includes word lines vertically stacked from a substrate, memory cells electrically connected to the word lines, a group controller configured to group the word lines into word line groups, and change the word line groups, based on electrical characteristics of the memory cells, and a voltage generator configured to store, in a voltage table, voltage values of operating voltages to be respectively applied to the word line groups.

Abstract: An apparatus includes a component coupleable to a memory device. The component can be configured to analyze a plurality of sets of memory cells of the memory device to determine quality attributes associated with the plurality of sets of memory cells and assign grades to one or more sets of the memory cells based, at least in part, on the determined quality attributes. The component can be configured to allocate at least one of the plurality of sets of memory cells for use by the memory device based, at least in part, on the assigned grade associated with the one or more sets of the memory cells.

Abstract: An apparatus includes a selection data generation circuit configured to generate selection data from fuse data or generate the selection data having a preset test input pattern, depending on whether a failure test is entered; and a failure flag generation circuit configured to generate latch data by latching the selection data, and generate a failure flag by detecting whether the latch data has a preset test pattern.

Abstract: The present disclosure includes apparatuses and methods related to defining activation functions for artificial intelligence (AI) operations. An example apparatus can include a number of memory arrays and a controller, wherein the controller includes a number of activations function registers, wherein the number of activation function registers define activation functions for artificial intelligence (AI) operations performed by the apparatus.

Abstract: Various embodiments of the present disclosure generally relate to a memory system and an operating method thereof. According to the embodiments of the disclosed technology, the memory system may check first information indicating an execution state of a reference operation on each of the memory blocks during a preset target time period, may determine, based on the first information, at least one target memory block, among the plurality of memory blocks, as a target of a refresh operation of rewriting data stored in the target memory block and may execute a refresh operation on the target memory block.

Abstract: A method of controlling a trajectory of a perpendicular magnetization switching of a ferromagnetic layer using spin-orbit torques in the absence of any external magnetic field includes: injecting a charge current Je through a heavy-metal thin film disposed adjacent to a ferromagnetic layer to produce spin torques which drive a magnetization M out of an equilibrium state towards an in-plane of a nanomagnet; turning the charge current Je off after te seconds, where an effective field experienced by the magnetization of the ferromagnetic layer Heff is significantly dominated by and in-plane anisotropy Hkx, and where M passes a hard axis by precessing around the Heff; and passing the hard axis, where Heff is dominated by a perpendicular-to-the-plane anisotropy Hkz, and where M is pulled towards the new equilibrium state by precessing and damping around Heff, completing a magnetization switching.

Abstract: A memory controller includes an interface and a processor. The interface communicates with a plurality of memory cells, and an individual one of the plurality of memory cells stores data in multiple predefined programming levels. The processor is configured to read an Error Correction Code (ECC) code word from a group of memory cells, via the interface, using multiple read thresholds positioned between adjacent programming levels, for producing multiple readouts that contain respective numbers of errors, to derive from the code word a reference readout that contains no errors, or contains a number of errors smaller than in the code word, to calculate multiple distances between the reference readout and the respective readouts, and set a preferred read threshold based on the calculated distances, and to perform subsequent read operations for retrieving data from the plurality of memory cells, using the preferred read threshold.

Abstract: A neural network computation circuit that outputs output data according to a result of a multiply-accumulate operation between input data and connection weight coefficients, the neural network computation circuit includes computation units in each of which a memory element and a transistor are connected in series between data lines, a memory element and a transistor are connected in series between data lines, and gates of the transistors are connected to word lines. The connection weight coefficients are stored into the memory elements. A word line selection circuit places the word lines in a selection state or a non-selection state according to the input data. A determination circuit determines current values flowing in data lines to output output data. A current application circuit has a function of adjusting current values flowing in data lines, and adjusts connection weight coefficients without rewriting the memory elements.

Abstract: Provided herein is a memory device and a method of operating the memory device. The memory device includes: a reference voltage generation circuit configured to generate a standby mode reference voltage in a standby mode, and generate and output an active mode reference voltage in an active mode; and an internal voltage generation circuit configured to receive the standby mode reference voltage or the active mode reference voltage from the reference voltage generation circuit, and generate an internal voltage. When an error is detected from the internal voltage generated in the standby mode, the reference voltage generation circuit may generate and output the active mode reference voltage.

Abstract: A storage device includes a memory, a write circuit, a read circuit, and a debug information register. The memory includes a data area and a redundant area that corresponds to the data area. The write circuit writes first data specified in a write command to the data area, and first information about a transmission source which has transmitted the write command, to the redundant area. The read circuit reads the first data as second data from the data area, and reads the first information as second information from the redundant area, in response to a read command. The debug information register stores the second information read by the read circuit.

Abstract: A base element for switching a magnetization state of a nanomagnet includes a heavy-metal nanostrip having a surface. The heavy-metal nanostrip includes at least a first layer including a heavy metal and a second layer which includes a different heavy-metal. A ferromagnetic nanomagnet is disposed adjacent to the surface. The ferromagnetic nanomagnet includes a shape having a long axis and a short axis, the ferromagnetic nanomagnet having both a perpendicular-to-the-plane anisotropy Hkz and an in-plane anisotropy Hkx and the ferromagnetic nanomagnet having a first magnetization equilibrium state and a second magnetization equilibrium state. The first magnetization equilibrium state or the second magnetization equilibrium state is settable by a flow of electrical charge through the heavy-metal nanostrip. A direction of the flow of electrical charge through the heavy-metal nanostrip includes an angle ? with respect to the short axis of the nanomagnet.

Abstract: A storage device includes 3D NAND including layers of multi-level cells. Test reads are performed by reading only LSB pages and reading layers in a repeating pattern of reading two and skipping two. A test read of a block is performed when its read count reaches a threshold. The counter threshold is updated according to errors detected during the test read such that the frequency of test reads increases with increase in errors detected. Counter thresholds according to errors may be specified in a table. The table may be selected as corresponding to a range of PEC values including the current PEC count of the 3D NAND. Each table further specifies a number of errors that will result in garbage collection being performed.

Abstract: A nonvolatile memory device includes a memory cell array having cell strings that each includes memory cells stacked on a substrate in a direction perpendicular to the substrate. A row decoder is connected with the memory cells through word lines. The row decoder applies a setting voltage to at least one word line of the word lines and floats the at least one word line during a floating time. A page buffer circuit is connected with the cell strings through bit lines. The page buffer senses voltage changes of the bit lines after the at least one word line is floated during the floating time and outputs a page buffer signal as a sensing result. A counter counts a number of off-cells in response to the page buffer signal. A detecting circuit outputs a detection signal associated with a defect cell based on the number of off-cells.

Abstract: Methods, systems, and devices for adjustable programming pulses for a multi-level cell are described. A memory device may modify a characteristic of a programming pulse for an intermediate logic state based on a metric of reliability of associated memory cells. The modified characteristic may increase a read window and reverse a movement of a shifted threshold voltage distribution (e.g., by moving the threshold voltage distribution farther from one or more other voltage distributions). The metric of reliability may be determined by performing test writes may be a quantity of cycles of use for the memory cells, a bit error rate, and/or a quantity of reads of the first state. The information associated with the modified second pulse may be stored in fuses or memory cells, or may be implemented by a memory device controller or circuitry of the memory device.

Abstract: A memory apparatus and method of operation is provided. The apparatus includes a block of memory cells. Each of the memory cells is connected to one of a plurality of word lines and are also arranged in strings and configured to retain a threshold voltage within a common range of threshold voltages. A control circuit coupled to the plurality of word lines and the strings is configured to determine an erase upper tail voltage of a distribution of the threshold voltage of the memory cells following an erase operation. The erase upper tail voltage corresponds to a cycling condition of the memory cells. The control circuit is also configured to calculate a program voltage to apply to each of selected ones of the plurality of word lines associated with the memory cells to program the memory cells during a program operation based on the erase upper tail voltage.

Abstract: Disclosed is a semiconductor device including first conductive lines, second conductive lines crossing the first conductive lines, and memory cells at intersections between the first conductive lines and the second conductive lines. Each of the memory cells includes a magnetic tunnel junction pattern, a bi-directional switching pattern connected in series to the magnetic tunnel junction pattern, and a conductive pattern between the magnetic tunnel junction pattern and the bi-directional switching pattern.