Patents Examined by Victor A. Mandala, Jr.
  • Patent number: 7566903
    Abstract: The present invention improves the aperture ratio of a pixel of a reflection-type display device or a reflection type display device without increasing the number of masks and without using a blackmask. A pixel electrode (167) is arranged so as to partially overlap a source wiring (137) for shielding the gap between pixels from light, and a thin film transistor is arranged so as to partially overlap a gate wiring (166) for shielding a channel region of the thin film transistor from light, thereby realizing a high pixel aperture ratio.
    Type: Grant
    Filed: November 28, 2005
    Date of Patent: July 28, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama
  • Patent number: 7544570
    Abstract: In a vertical-type metal insulator field effect transistor device having a first conductivity type drain region layer, a plurality of second conductivity type base regions are produced and arranged in the first conductivity type drain region layer, and a first conductivity type source region is produced in each of the second conductivity type base regions. Both a gate insulating layer and a gate electrode layer are formed on the first conductivity type drain region layer such that a plurality of unit transistor cells are produced in conjunction with the second conductivity type base regions and the first conductivity type source regions, and each of the unit transistor cells includes respective span portions of the gate insulating layer and the gate electrode layer, which bridge a space between the first conductivity type source regions formed in two adjacent second conductivity base regions.
    Type: Grant
    Filed: October 3, 2006
    Date of Patent: June 9, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Kinya Ohtani
  • Patent number: 7504715
    Abstract: The present invention is directed to an interposer for packaging a microchip device, which includes a plurality of electrical contacts on an outer side of the interposer, for electrically contacting the packaged microchip device and to be electrically connected with the microchip device. There is an aperture extending from the outer side into the interposer. The aperture may be divided into at least two openings, and at least a first of the openings may extend from the outer side through the interposer in order to allow connection to the microchip device.
    Type: Grant
    Filed: September 21, 2006
    Date of Patent: March 17, 2009
    Assignee: United Test & Assembly Center Limited
    Inventor: Wang Chuen Khiang
  • Patent number: 7462881
    Abstract: A method of fabricating semiconductor devices, such as GaN LEDs, on insulating substrates, such as sapphire. Semiconductor layers are produced on the insulating substrate using normal semiconductor processing techniques. Trenches that define the boundaries of the individual devices are then formed through the semiconductor layers and into the insulating substrate, beneficially by using inductive coupled plasma reactive ion etching. The trenches are then filled with an easily removed layer. A metal support structure is then formed on the semiconductor layers (such as by plating or by deposition) and the insulating substrate is removed. Electrical contacts, a passivation layer, and metallic pads are then added to the individual devices, and the individual devices are then diced out.
    Type: Grant
    Filed: August 30, 2007
    Date of Patent: December 9, 2008
    Assignee: LG Electronics Inc.
    Inventors: Jong-Lam Lee, In-kwon Jeong, Myung Cheol Yoo
  • Patent number: 7459328
    Abstract: An image sensor for minimizing a dark level defect is disclosed. The image sensor includes an isolation layer formed on a substrate. A field region and an active region are defined on the substrate by the isolation layer. A photodiode is formed in the image sensor in such a structure that a first region is formed below a surface of the substrate in the active region and a second region is formed under the first region. A first conductive type impurity is implanted into the first region and a second conductive type impurity is implanted into the second region. A dark current suppressor is formed on side and bottom surfaces of the isolation layer adjacent to the first region, and the dark current suppressor is doped with the second conductive type impurity. The dark current suppressor suppresses the dark current to minimize the dark level defect caused by the dark current.
    Type: Grant
    Filed: February 12, 2008
    Date of Patent: December 2, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Sang-Il Jung
  • Patent number: 7456491
    Abstract: The present invention relates to a various systems for generating and directing electron flow, and related methods, manufacturing techniques and related componentry, such as can be used in lithography, microscopy and other applications. In one embodiment, the present invention involves a system that includes an electron source having a plurality of independently-actuatable emission surfaces each of which is capable of emitting electrons, and an optical column adjacent to the electron source through which the emitted electrons pass. The optical column includes a plurality of actuatable electrodes that are capable of influencing paths taken by the emitted electrons.
    Type: Grant
    Filed: July 22, 2005
    Date of Patent: November 25, 2008
    Inventor: Subrahmanyam V. S. Pilla
  • Patent number: 7436037
    Abstract: A differential pressure sensor has a semiconductor wafer having a top and bottom surface. The top surface of the wafer has a central active area containing piezoresistive elements. These elements are passivated and covered with a layer of silicon dioxide. Each element has a contact terminal associated therewith. The semiconductor wafer has an outer peripheral silicon frame surrounding the active area. The semiconductor wafer is bonded to a glass cover member via an anodic or electrostatic bond by bonding the outer peripheral frame to the periphery of the glass wafer. An inner silicon dioxide frame forms a compression bond with the glass wafer when the glass wafer is bonded to the silicon frame. This compression bond prevents deleterious fluids from entering the active area or destroying the silicon. The above described apparatus is mounted on a header such that through holes in the glass wafer are aligned with the header terminals.
    Type: Grant
    Filed: January 10, 2007
    Date of Patent: October 14, 2008
    Assignee: Kulite Semiconductor Products, Inc.
    Inventors: Anthony D. Kurtz, Alexander A. Ned
  • Patent number: 7432571
    Abstract: Provided are a multi-scale cantilever structure having nano-sized holes prepared by anodic oxidation and a method of preparing the same. The multi-scale cantilever structure is prepared using anodic oxidation and electro-polishing so that a manufacturing process is simple and a manufacturing cost is inexpensive. In addition, the multi-scale cantilever structure has a porous structure having a plurality of nano-sized holes inside thereof, and thus a surface area of the cantilever structure can be maximized. Therefore, when the cantilever structure is used in a sensor, the sensor can have improved sensitivity and selectivity.
    Type: Grant
    Filed: October 26, 2006
    Date of Patent: October 7, 2008
    Assignees: Postech Foundation, Postech Academy-Industry Foundation
    Inventors: Jung Hyun Lee, Pyung Soo Lee, Kun Hong Lee, Nayoung Shin
  • Patent number: 7432554
    Abstract: A complementary metal oxide semiconductor (CMOS) thin film transistor including a common gate, a logic device including the CMOS thin film transistor, and a method of manufacturing the CMOS thin film transistor are provided. In one embodiment, the CMOS thin film transistor includes a base substrate and a semiconductor layer formed on the base substrate. A PMOS transistor and an NMOS transistor are formed on a single semiconductor layer to intersect each other, and a common gate is formed on the intersection area. In addition, a Schottky barrier inducing material layer is formed on a source and a drain of the PMOS transistor.
    Type: Grant
    Filed: December 16, 2005
    Date of Patent: October 7, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Moon-Kyung Kim, Jo-Won Lee, Yoon-Dong Park, Chung-Woo Kim
  • Patent number: 7425730
    Abstract: In an organic electro-luminescent display, a pixel circuit is disposed in a unit pixel region defined on a substrate. A passivation layer covers the entire unit pixel region including the pixel circuit. An organic light emitting diode (“OLED”) including a transparent lower electrode formed on a portion of the passivation layer which does not overlap the pixel circuit, an OLED layer, and an upper electrode are sequentially formed on the passivation layer. The transparent lower electrode is a transparent anode of the OLED. A protective layer is formed of the same material as the transparent lower electrode and disposed on a portion of the passivation layer corresponding to the pixel circuit to cover and protect the pixel circuit.
    Type: Grant
    Filed: November 1, 2006
    Date of Patent: September 16, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho-nyeon Lee, Sung-kee Kang, Jung-woo Kim, Ick-hwan Ko, Young-gu Lee, Hong-shik Shim
  • Patent number: 7425767
    Abstract: A semiconductor chip or wafer comprises a passivation layer and a circuit line. The passivation layer comprises an inorganic layer. The circuit line is over and in touch with the inorganic layer of the passivation layer, wherein the circuit line comprises a first contact point connected to only one second contact point exposed by an opening in the passivation layer, and the positions of the first contact point and the only one second contact point from a top view are different, and the first contact point is used to be wirebonded thereto.
    Type: Grant
    Filed: September 26, 2007
    Date of Patent: September 16, 2008
    Assignee: Megica Corporation
    Inventor: Mou-Shiung Lin
  • Patent number: 7424136
    Abstract: A finger sensor may include a finger sensing integrated circuit (IC) having a finger sensing area, an IC carrier having a cavity receiving the finger sensing IC therein and having at least one beveled upper edge, and a frame surrounding at least a portion of an upper perimeter of the IC carrier and having at least one inclined surface corresponding to the at least one beveled upper edge of the IC carrier. The finger sensor may also include a biasing member for biasing the IC carrier into alignment within the frame. The biasing member may include at least one resilient body for biasing the IC carrier upward within the frame. In other embodiments, the finger sensor may include an IC carrier having a cavity receiving the finger sensing IC therein and having at least one laterally extending projection.
    Type: Grant
    Filed: October 18, 2006
    Date of Patent: September 9, 2008
    Assignee: Authentec, Inc.
    Inventors: Dale R. Setlak, Matthew M. Salatino, Philip J. Spletter, Yang Rao
  • Patent number: 7420207
    Abstract: A photo-detecting device includes a buried doping layer of a first conductivity type and disposed at an upper portion of a silicon substrate. A first silicon epitaxial layer of first conductivity type is disposed on the buried doping layer, and a second silicon epitaxial layer of second conductivity type is disposed on the first silicon epitaxial layer. An isolation doping layer doped of first conductivity type is disposed at a predetermined region of the second silicon epitaxial layer to define a body region of second conductivity type. A silicon germanium epitaxial layer of second conductivity type is disposed on the body region.
    Type: Grant
    Filed: December 19, 2005
    Date of Patent: September 2, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-Jin Kim, Kwang-Joon Yoon, Phil-Jae Chang, Kye-Won Maeng, Young-Jun Park
  • Patent number: 7420221
    Abstract: A semiconductor light-emitting device includes: a semiconductor multilayer film, a substrate supporting the semiconductor multilayer film; and a phosphor layer formed on the substrate so as to cover the semiconductor multilayer film. The phosphor layer has an outer edge of a cross section taken in a direction parallel to the principal surface of the substrate having a substantially circular shape or a substantially regular polygonal shape having five or more sides. An outer edge of the principal surface of the substrate is formed in a substantially circular shape or a substantially regular polygonal shape having five or more sides. With this configuration, light obtained therefrom has less non-uniformity in color and a high luminous flux can be realized.
    Type: Grant
    Filed: September 1, 2005
    Date of Patent: September 2, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Hideo Nagai
  • Patent number: 7417326
    Abstract: A semiconductor device includes a plurality of electrode layers provided at designated positions of a semiconductor substrate, an organic insulation film formed on the semiconductor substrate by selectively exposing designated areas of the electrode layers, and projection electrodes for outside connection, the projection electrodes being formed on the designated areas of the electrode layers. Thickness of the organic insulation film situated in the vicinity of the periphery of the projection electrodes is greater than thickness of the organic insulation film situated between the projection electrodes.
    Type: Grant
    Filed: March 14, 2006
    Date of Patent: August 26, 2008
    Assignee: Fujitsu Limited
    Inventors: Masamitsu Ikumo, Hiroyuki Yoda, Eiji Watanabe
  • Patent number: 7414290
    Abstract: A double gate transistor comprises a substrate (105, 905) and first and second electrically insulating layers (110, 910), (120, 920). The first and second electrically insulating layers form a fin (130, 930). A first gate dielectric (140,940) is at a first side (131, 931) of the fin and a second gate dielectric (150, 950) is at a second side (132, 932) of the fin. A first metal region (160, 960) is adjacent to the first gate dielectric and has a first surface (161, 961), and a second metal region (170, 970) is adjacent to the second gate dielectric and has a second surface (171, 971). The first electrically insulating layer has a third surface (111, 911), the second electrically insulating layer has a fourth surface (121, 921), and the first surface and the second surface lie between the third and fourth surfaces.
    Type: Grant
    Filed: June 23, 2006
    Date of Patent: August 19, 2008
    Assignee: Intel Corporation
    Inventors: Ibrahim Ban, Uday Shah
  • Patent number: 7414258
    Abstract: A memory device comprising a first pan-shaped electrode having a side wall with a top side, a second pan-shaped electrode having a side wall with a top side and an insulating wall between the first side wall and the second side wall. The insulating wall has a thickness between the first and second side walls near the respective top sides. A bridge of memory material crosses the insulating wall, and defines an inter-electrode path between the first and second electrodes across the insulating wall. An array of such memory cells is provided. The bridges of memory material have sub-lithographic dimensions.
    Type: Grant
    Filed: June 14, 2006
    Date of Patent: August 19, 2008
    Assignee: Macronix International Co., Ltd.
    Inventors: Hsiang Lan Lung, Shih-Hung Chen
  • Patent number: 7408249
    Abstract: A packaged integrated circuit and method for producing thereof, including an integrated circuit substrate lying in a substrate plane and having electrical circuitry formed thereon, a package enclosing the integrated circuit substrate and defining first and second planar surfaces generally parallel to the substrate plane and a plurality of electrical contacts, each connected to the electrical circuitry at the substrate plane, at least some of the plurality of electrical contacts extending onto the first planar surface and at least some of the plurality of electrical contacts extending onto the second planar surface.
    Type: Grant
    Filed: December 19, 2001
    Date of Patent: August 5, 2008
    Assignee: Tessera Technologies Hungary Kft.
    Inventor: Avner Badihi
  • Patent number: RE40705
    Abstract: A high-breakdown-voltage semiconductor apparatus is provided, wherein when a gate capacitance of that portion of a gate electrode, under which a channel is formed, is Cg [F], a resistance in a channel length direction of that portion of the gate electrode, under which the channel is formed, is Rg [?], a threshold voltage, which is to be applied to the gate electrode and application of which permits flow of a drain current, is Vth [V], a voltage to be applied to the gate electrode to cut off the drain current is Voff [V], and a ratio of increase in the drain voltage per unit time at the time of cutting off the drain current is dV/dt [V/s], the following condition is satisfied: |Vt?Voff|?0.5·Cg·Rg·(dV/dt).
    Type: Grant
    Filed: March 21, 2002
    Date of Patent: May 5, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuya Nakayama, Koichi Sugiyama
  • Patent number: RE40712
    Abstract: A high-breakdown-voltage semiconductor apparatus is provided, wherein when a gate capacitance of that portion of a gate electrode, under which a channel is formed, is Cg[F], a resistance in a channel length direction of that portion of the gate electrode, under which the channel is formed, is Rg [?], a threshold voltage, which is to be applied to the gate electrode and application of which permits flow of a drain current, is Vth [V], a voltage to be applied to the gate electrode to cut off the drain current is Voff [V], and a ratio of increase in the drain voltage per unit time at the time of cutting off the drain current is dV/dt [V/s], the following condition is satisfied: |Vth?Voff|?0.
    Type: Grant
    Filed: February 19, 2003
    Date of Patent: May 19, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuya Nakayama, Koichi Sugiyama