Abstract: The invention relates to a memory module having a printed circuit board; having one or more memory chips which are arranged in a first region of the printed circuit board and are contact-connected by the printed circuit board; having a buffer chip for driving the memory chips and for communicating with a system that is external to the memory module, the buffer chip being arranged in a second region of the printed circuit board and being contact-connected by the printed circuit board; wherein the first and second regions of the printed circuit board are essentially thermally decoupled from one another.

Abstract: A plurality of gate lines are formed on a substrate. After depositing a gate insulating layer, a semiconductor layer and a doped amorphous silicon layer are sequentially formed thereon. A lower insulating layer made of silicon nitride and an upper insulating layer made of a photosensitive organic material are deposited thereon after forming data lines and drain electrodes. The upper insulating layer is patterned to form an unevenness pattern on its surface and contact holes on the drain electrodes. The lower insulating layer is patterned together with the gate insulating layer using a photoresist pattern having apertures located in the contact holes to form other contact holes respectively exposing the drain electrodes, portions of the gate lines, and portions of the data lines.

Abstract: A semiconductor substrate integrated with interconnections and circuit components. A silicon backplane is processed with silicon processing to provide electrical connectivity for circuit elements. In one embodiment functional circuit elements, e.g., MEMS, switches, filters, are integrated on the silicon backplane. In one embodiment the function circuit elements are monolithically processed into the silicon backplane. In one embodiment the silicon backplane includes interconnections for integrated circuits on different substrates to be bonded to the silicon backplane.

Abstract: A device using an ambipolar transport of an SB-MOSFET and a method for operating the same are provided. The SB-MOSFET includes: a silicon channel region; a source and a drain contacted on both sides of the channel region and formed of material including metal layer; and a gate formed on the channel region, with a gate dielectric layer interposed therebetween. Positive (+), 0 or negative (?) gate voltage is selectively applied to the gate, the channel becomes off-state when the gate voltage between a negative threshold voltage and a positive threshold voltage is applied, and the channel becomes a first on-state and a second on-state when the gate voltage is lower than the negative threshold voltage or higher than the positive threshold voltage. Accordingly, it is possible to implement three current states, that is, hole current, electron current, and no current. The SB-MOSFET can be applied to a multi-bit memory and/or multi-bit logic device.

Abstract: The present invention is a semiconductor device capable of relieving thermal stress without breaking wire. It comprises a semiconductor chip (12), a solder ball (20) for external connection, wiring (18) for electrically connecting the semiconductor chip (12) and the solder ball (20), a stress relieving layer (16) provided on the semiconductor chip (12), and a stress transmission portion (22) for transmitting stress from the solder ball (20) to the stress relieving layer (16) in a peripheral position of an electrical connection portion (24a) of the solder ball (20) and wiring (18).

Abstract: A highly integrated radio front-end module. In one embodiment a semiconductor substrate is processed with various circuit components in the substrate, as well as interconnections for the various circuit components, embedding the circuit components into the substrate. One or more circuit components may be further connected with a separate integrated circuit, the separate integrated circuit bonded to the semiconductor substrate via contact points processed into the substrate.

Abstract: A multiple IC package module comprises a plurality of IC devices inserted in associated sockets mounted on a substrate. Each IC device has opposed, major surfaces, one of the major surfaces of each device confronting the socket into which the device is inserted. A compressible compliance layer is interposed between the one major surface of each IC device and the associated socket into which the IC device is inserted. The module further comprises a single heat sink having a surface in heat transfer relationship with the other of the major surfaces of the IC devices. Also disclosed is an IC device package comprising an IC device including interconnect pins projecting from the device, a socket comprising contact receptacles for receiving the interconnect pins, and a compressible compliance layer interposed between the IC device and the socket, the interconnect pins projecting through the compliance layer and into the contact receptacles in the socket.

Abstract: Various embodiments of the present invention are directed to crossbar array designs that interfaces wires to address wires, despite misalignments between electrical components and wires. In one embodiment, a nanoscale device may be composed of a first layer of two or more wires and a second layer of two or more address wires that overlays the first layer. The nanoscale device may also include an intermediate layer positioned between the first layer and the second layer. Two or more redundant electrical component patterns may be fabricated within the intermediate layer so that one or more of the electrical component patterns is aligned with the first and second layers.

Abstract: A lead frame may include a plurality of leads, each having a bonding portion electrically connected to a semiconductor chip and an attaching portion. A tape may be provided on the attaching portions of the leads. The attaching portion of each lead may have a width that is smaller than the width of another portion of the lead. A plating layer may be provided on the attaching portion. The lead frame may be implemented in a semiconductor package.

Abstract: A vertical-conduction and planar-structure MOS device having a double thickness gate oxide includes a semiconductor substrate including spaced apart active areas in the semiconductor substrate and defining a JFET area therebetween. The JFET area also forms a channel between the spaced apart active areas. A gate oxide is on the semiconductor substrate and includes a first portion having a first thickness on the active areas and at a periphery of the JFET area, and a second portion having a second thickness on a central area of the JFET area. The second thickness is greater than the first thickness. The JFET area also includes an enrichment region under the second portion of the gate oxide.

Abstract: The present invention proposes an organic photovoltaic component, particularly an organic solar cell, whose electrode is implemented as unstructured and is provided with a passivation layer, so that the passivated electrode layer acts functionally as a structured electrode or electrode layer.

Abstract: Disclosed herein are novel support structures for pad reinforcement in conjunction with new bond pad designs for semiconductor devices. The new bond pad designs avoid the problems associated with probe testing by providing a probe region that is separate from a wire bond region. Separating the probe region 212 from the wire bond region 210 and forming the bond pad 211 over active circuitry has several advantages. By separating the probe region 212 from the wire bond region 210, the wire bond region 210 is not damaged by probe testing, allowing for more reliable wire bonds. Also, forming the bond pad 211 over active circuitry, including metal interconnect layers, allows the integrated circuit to be smaller.

Abstract: A surface acoustic wave device has a SAW device element 10 and a package 20 housing the SAW device element. The package includes a resin substrate 20 having metal patterns 21 and 22 formed on both surfaces thereof, and a resin cap 32. The SAW device element is mounted on one of the metal patterns of the resin substrate. The resin cap is adhered to the resin substrate to cover the SAW device element. The surfaces of the resin substrate are flush with corresponding end surfaces of the resin cap.

Abstract: A semiconductor device includes a semiconductor substrate in which an integrated circuit is formed and which includes interconnects and electrodes, the interconnects electrically connected with the semiconductor substrate, and the electrodes being formed on the interconnects; a resin layer formed on the semiconductor substrate; redistribution interconnects electrically connected with the electrodes; a plurality of external terminals which are formed on the redistribution interconnects and supported by the resin layer; and a plurality of dummy terminals supported by the resin layer without being electrically connected with the electrodes.

Abstract: An electrically stable PbLa0.5TiO3/PbZr0.52Ti0.48O3 (PLT/PZT) ferroelectric structure may fabricated using precursor solutions formed using a simple sol-gel process. The PLT/PZT ferroelectric structure may be extended to a PLT/PZT/PLT ferroelectric capacitor structure. In terms of device application, better ferroelectric properties with reliable fatigue characteristics are desirable to render satisfactory performance and long device life. The PLT/PZT/PLT ferroelectric capacitor structure excels over previous hybrid structures by providing a larger remnant polarization, higher saturation polarization, lower coercive field and leakage current density and higher resistance to fatigue. The fabrication method involving the use of a PLT seeding layer acts to lower the fabrication temperature of the subsequent PZT layer and allows for a simpler sequence of processing steps that may be seen to substantially reduce manufacturing costs.

Abstract: A molding compound cap structure is disclosed. A process of forming the molding compound cap structure is also disclosed. A microelectronic package is also disclosed that uses the molding compound cap structure. A method of assembling a microelectronic package is also disclosed. A computing system is also disclosed that includes the molding compound cap structure. The molding compound cap includes a configuration that exposes a portion of a microelectronic device.

Abstract: The present invention provides a QFN package structure, comprising a chip carrier and at least a chip. The chip is disposed on the top surface of the chip carrier, while the back surface of the chip carrier includes a plurality of flat no-lead conductive leads as I/O pads of the chip carrier for the external circuitry. A plurality of pads, corresponding to bonding pads of the chip, is disposed on the top surface of the chip carrier. The aforementioned package structure can employ wiring bonding technology, flip chip technology or surface mount technology to attach the chip to the chip carrier.

Abstract: A semiconductor device comprising a first insulation layer, a second insulation layer, a first barrier film, a second barrier film, a diffusion layer. The device further comprises an upper contact hole, a lower contact hole, and a contact plug. The upper contact hole penetrates the second insulation layer and has a bottom in the second barrier film. The bottom has a width greater than a trench made in the first insulation layer, as measured in a direction crossing the widthwise direction of the trench. The lower contact hole penetrates the first insulation layer and first barrier film, communicates with the first contact hole via the trench and is provided on the diffusion layer. The upper portion of the lower contact hole has the same width as the trench. The contact plug is provided in the upper contact hole and lower contact hole.

Abstract: One aspect of the present subject matter relates to a partially depleted silicon-on-insulator structure. The structure includes a well region formed above an oxide insulation layer. In various embodiments, the well region is a multilayer epitaxy that includes a silicon germanium (Si—Ge) layer. In various embodiments, the well region includes a number of recombination centers between the Si—Ge layer and the insulation layer. A source region, a drain region, a gate oxide layer, and a gate are formed. In various embodiments, the Si—Ge layer includes a number of recombination centers in the source/drain regions. In various embodiments, a metal silicide layer and a lateral metal Schottky layer are formed above the well region to contact the source region and the well region. Other aspects are provided herein.

Abstract: A wire connection structure for an integrated circuit (IC) die includes a semiconductor wafer with an active device and/or a passive device. One or more dielectric layers are arranged adjacent to the active and/or passive device. One or more metal interconnect layers are arranged adjacent to the active and/or passive device. A contact pad is arranged in an outermost metal interconnect layer. A passivation layer is arranged over the outermost metal interconnect layer and includes at least one passivation opening that exposes the contact pad. A bond pad is arranged over the passivation layer and the active and/or passive device and is connected to the contact pad through the passivation opening. Formation of the bond pad does not damage the active and/or passive device.