Abstract: The invention concerns a matrix structure of multispectral detectors (200) comprising: a superimposition of several layers of semiconductor material separated by layers of dielectric material transparent to a light to be detected, said superimposition offering a face for receiving the light to be detected, said superimposition of layers of semiconductor material being spread out in picture elements or pixels, each part of the layer of semiconductor material corresponding to a pixel comprising a light detection element delivering electrical charges in response to the light received by said detection element, means for collecting the electrical charges delivered by each light detection element, said collection means being electrically connected to electrical connection means (153) and comprising conductive walls (151).

Abstract: A liquid metal thermal interface for an integrated circuit die. The liquid metal thermal interface may be disposed between the die and another heat transfer element, such as a heat spreader or heat sink. The liquid metal thermal interface includes a liquid metal in fluid communication with a surface of the die, and liquid metal moving over the die surface transfers heat from the die to the heat transfer element. A surface of the heat transfer element may also be in fluid communication with the liquid metal. Other embodiments are described and claimed.

Abstract: An electrostatic discharge protection network that uses triple well semiconductor devices either singularly or in a series configuration. The semiconductor devices are preferably in diode junction type configuration.

Abstract: A semiconductor material which has a high carbon dopant concentration includes gallium, indium, arsenic and nitrogen. The disclosed semiconductor materials have a low sheet resistivity because of the high carbon dopant concentrations obtained. The material can be the base layer of gallium arsenide-based heterojunction bipolar transistors and can be lattice-matched to gallium arsenide emitter and/or collector layers by controlling concentrations of indium and nitrogen in the base layer. The base layer can have a graded band gap that is formed by changing the flow rates during deposition of III and V additive elements employed to reduce band gap relative to different III-V elements that represent the bulk of the layer. The flow rates of the III and V additive elements maintain an essentially constant doping-mobility product value during deposition and can be regulated to obtain pre-selected base-emitter voltages at junctions within a resulting transistor.

Abstract: Disclosed are a multi-threshold CMOS circuit and a method of designing such a circuit. The preferred embodiment combines an MTCMOS scheme and a hybrid SOI-epitaxial CMOS structure. Generally, the logic transistors (both nFET and pFET) are placed in SOI, preferably in a high-performance, high density UTSOI; while the headers or footers are made of bulk epitaxial CMOS devices, with or without an adaptive well-biasing scheme. The logic transistors are based on (100) SOI devices or super HOT, the header devices are in bulk (100) or (110) pFETs with or without an adaptive well biasing scheme, and the footer devices are in bulk (100) NFET with or without an adaptive well biasing scheme.

Abstract: A semiconductor device includes plural electrode pads arranged in an active region of a semiconductor chip, and wiring layers provided below the plural electrode pads wherein occupation rates of wirings arranged within the regions of the electrode pads are, respectively, made uniform for every wiring layer. To this end, in a region where an occupation rate of wiring is smaller than those in other regions, a dummy wiring is provided. On the contrary, when the occupation rate of wiring is larger than in other regions, slits are formed in the wiring to control the wiring occupation rate. In the respective wirings layers, the shapes, sizes and intervals of wirings below the respective electrode pads are made similar or equal to one another.

Abstract: A light emitting diode includes a casing having a concave surface, a reflecting surface formed by depositing a metallic layer on a concave surface thereof, and a lead having a light emitting element fitted thereto so as to confront the reflecting surface. A cationic polymerization type transparent epoxy resin is filled within a cavity of the casing having the concave surface, and the resin is hardened while the resin, the reflecting surface and the casing form a sandwich structure. With this construction, the light emitting diode is provided, in which neither wrinkling nor cracking occur in the reflecting surface. In addition, there is no possibility of the reflecting surface being flawed during the handling and transportation. Also, even in a reflow furnace operation in which a soldering is carried out, thermal deformation including formation of wrinkling and cracking in the reflecting surface can be completely avoided.

Abstract: An optical element comprising: a surface-emitting type semiconductor laser having an emission surface; and a photodetector element formed above the emission surface of the surface-emitting type semiconductor laser, wherein the photodetector element includes a semiconductor layer having a photoabsorption layer, the semiconductor layer having a film thickness d that satisfies a formula (1) as follows: (2m?1)?/4n?3?/16n<d<(2m?1)?/4n+3?/16n . . . , ??(1) where m is an integer, n is a refractive index of the semiconductor layer, and ? is a designed wavelength of the surface-emitting type semiconductor laser.

Abstract: A method, apparatus and system with a semiconductor package including a microchimney or thermosiphon using carbon nanotubes to modify the effective thermal conductivity of an integrated circuit die.

Abstract: A phase change memory element and methods for forming the same are provided. The memory element includes a first electrode and a chalcogenide comprising phase change material layer over the first electrode. A metal-chalcogenide layer is over the phase change material layer. The metal chalcogenide layer is tin-telluride. A second electrode is over the metal-chalcogenide layer. The memory element is configured to have reduced current requirements.

Abstract: Systems and methods are disclosed to process a semiconductor substrate by fabricating a first layer on the substrate using semiconductor fabrication techniques; fabricating a second layer above the first layer having one or more NANO-bonding areas; self-assemblying one or more NANO-elements; and bonding the NANO-elements to the NANO-bonding areas.

Abstract: A split-gate flash memory process for improving sharpness and height of a floating-gate tip has steps as follows. Using a dry etching process, a trench is formed in the first polysilicon layer through the pattern opening. An oxide layer is then deposited on the first polysilicon layer through a CVD process to fill the trench. Through a CMP process, portions of the oxide layer are removed to substantially planarize the trench-filled oxide layer as the first polysilicon layer. Using a dry etching process with the trench-filled oxide layer with a mask, the first polysilicon layer is patterned as a floating gate, and the corner edge of the floating gate has a polysilicon tip.

Abstract: The present invention is related to a light emitting diode of an omnidirectional reflector providing with a transparent conductive layer. In the present invention, a cohesion layer is formed between a transparent layer and a metal reflection layer to improve the cohesive force therebetween and increase the reflectivity of the light emitting diode, so as the present invention can enhance the light-emitting efficiency of the light emitting diode.

Abstract: A trench (2) is fabricated in a silicon body (1). The walls (4) of the trench are provided with a nitrogen implantation (6). An oxide layer between the source/drain regions (5) and a word line applied on the top side grows to a greater thickness than a lower oxide layer of an ONO storage layer fabricated as gate dielectric at the trench wall. Instead of the nitrogen implantation into the trench walls, it is possible to fabricate a metal silicide layer on the top sides of the source/drain regions in order to accelerate the oxide growth there.

Abstract: A semiconductor device includes an ONO film (17) formed on a semiconductor substrate (15), a first gate (14), the first gate (14) formed on the ONO film (17), a source (10) and a drain (12) provided at both sides of the first gate (14) to face each other, and a second gate (16), the second gate (16) being a side gate provided at a side of the first gate (14) other than the side where the source (10) and the drain (12) are provided. This makes it possible to provide the semiconductor device in which a desired circuit characteristic is obtainable in a non-destructive manner and in a non-volatile fashion while reducing the trial production times thereof for IC development.

Abstract: A multilevel metal and via structure is described. The metal conductors include a base or seed layer, a bulk conductor layer, a capping layer, and a barrier layer, and the via structure include a seed layer, a diffusion barrier layer and a metal plug. The via seed layer is controlled to a thickness that discourages the reaction between the via seed layer and the bulk conductor layer. The reaction may result in the formation of harmful voids at the bottom of the vias and is caused by having the via seed metal coming in contact with the bulk conductor through openings in the barrier layer.

Abstract: In a high voltage P-channel MOS transistor formed on a silicon-on-insulator (SOI) substrate, a P+-type source region (8), an N-type body region (4) and an N+-body contact diffusion region (10) are surrounded by a P+-type drain region (9) and a P-type drift region (5). A gate electrode (7) is formed to overlap the end portion of the N-type body region (4). The end portion of the N-type body region (4) has a portion in which the gate electrode (7) and the P+-type source region (8) are not adjacent to each other.

Abstract: The present invention provides an efficient test method and system for testing the IC package, such as BGA types of packages. With the present invention, manufacturer can have an easier way in testing various types of packages, including newer types. Manufacturer also can get the testing outcome which is more accurate. Furthermore, the present invention helps the manufacturer achieve a significant improvement in an IC packaging process.

Abstract: A semiconductor chip or wafer comprises a passivation layer and a circuit line. The passivation layer comprises an inorganic layer. The circuit line is over and in touch with the inorganic layer of the passivation layer, wherein the circuit line comprises a first contact point connected to only one second contact point exposed by an opening in the passivation layer, and the positions of the first contact point and the only one second contact point from a top view are different, and the first contact point is used to be wirebonded thereto.

Abstract: A lens assembly for sideward light emission includes a lens and a lens cap. The lens has a cup portion, an open end portion, and first and second refracting portions. The cup portion surrounds a light source. The open end portion defines an opening. The first refracting portion interconnects the cup portion and the open end portion. The second refracting portion is disposed in the lens and is formed on the first refracting portion. The lens cap is mounted to the open end portion of the lens for covering the opening.