Abstract: A method of forming an isolation structure, wherein a hard mask is formed on a first region and a second region of a substrate; the substrate is etched using the hard mask as an etching mask to form a plurality of first active patterns in the first region and a plurality of second active patterns in the second region, a first trench between the first active patterns having a first trench width, and a second trench between the second active patterns having a second trench width smaller than the first trench width; a first oxide layer is formed on the hard mask and the first and second trenches; the first oxide layer is conformally formed on an inner wall of the first trench and filling the second trench; a polysilicon layer is conformally formed on the first oxide layer and a spin-on-dielectric (SOD) layer is formed on the polysilicon layer to fill the first trench; and the SOD layer and the polysilicon layer are annealed using an oxygen-containing gas so that the SOD layer and the polysilicon layer are transf

Abstract: A package includes a first package component, a second package component over the first package component, and a solder region bonding the first package component to the second package component. At least one ball-height control stud separates the first package component and the second package component from each other, and defines a standoff distance between the first package component and the second package component.

Abstract: A method of manufacturing an organic light emitting display includes forming a first light-emitting layer on a substrate, forming a first portion of a second light-emitting layer on the first light-emitting layer, forming a third light-emitting layer on the first light-emitting layer, and forming a second portion of the second light-emitting layer on the first portion of the second light-emitting layer.

Abstract: A thin film transistor (TFT) substrate includes an insulating layer, an electrode on the insulating layer, and a main buffering layer connecting a side surface of the electrode to an upper surface of the insulating layer.

Abstract: A semiconductor substrate includes a drift region and a collector region. The drift region is provided across an active area, an interface area, and an edge termination area. The collector region is provided only in the active area and forms part of a second surface. An emitter electrode is provided in the active area and contacts a first surface of the semiconductor substrate. A collector electrode is provided on the second surface of the semiconductor substrate and contacts the collector region.

Abstract: The method includes prior to depositing a gate on a first vertical FET on a semiconductor substrate, depositing a first layer on the first vertical FET on the semiconductor substrate. The method further includes prior to depositing a gate on a second vertical FET on the semiconductor substrate, depositing a second layer on the second vertical FET on the semiconductor substrate. The method further includes etching the first layer on the first vertical FET to a lower height than the second layer on the second vertical FET. The method further includes depositing a gate material on both the first vertical FET and the second vertical FET. The method further includes etching the gate material on both the first vertical FET and the second vertical FET to a co-planar height.

Abstract: A semiconductor process for providing a metal layer uses the following steps: A barrier dielectric layer is deposited on a semiconductor layer comprising an exposed metal line. A via layer is formed on top of the barrier dielectric layer comprising at least one via. A non-conformal film is deposited on top of the via layer thereby forming a void in the at least one via, and at least one trench is etched into the non-conformal film thereby opening the void, and creating a dual-damascene layer.

Abstract: A semiconductor device includes a substrate, a drift region, a source region, a gate region, a drain contact and a base region. The substrate is doped with a first dopant type. The drift region is disposed above the substrate, and is doped with the first dopant type. The source region, doped with the first dopant type. The gate region is disposed above the drift region and above the source region. The base region is disposed between the source region and the drift region. At least a portion of the base region includes at least one trench having a vertical wall and a horizontal wall. The base region is further configured to conduct current in a horizontal direction on the vertical wall and in a horizontal direction the horizontal wall.

Abstract: An apparatus comprises a substrate including a surface and a plurality of bonding pads positioned on the surface. The apparatus also includes a material comprising a solder positioned on the bonding pads and extending a distance outward therefrom. A first of the bonding pads in a first location on the substrate surface includes the solder extending a first distance outward therefrom. A second of the bonding pads in a second location on the substrate surface includes the solder extending a second distance outward therefrom. The first distance is different than the second distance. Other embodiments are described and claimed.

Abstract: A method of manufacturing an SOI wafer, including (a) forming a thermal oxide film on an SOI layer of an SOI wafer by a heat treatment under an oxidizing gas atmosphere, (b) measuring thickness of the SOI layer after forming the thermal oxide film, (c) performing a batch cleaning, wherein an etching amount of SOI layer is adjusted depending on thickness of the SOI layer measured in step (b) such that thickness of the SOI layer is adjusted to be thicker than a target value after etching, (d) measuring thickness of the SOI layer after batch cleaning, (e) performing a single-wafer cleaning, wherein an etching amount of the SOI layer is adjusted depending on thickness of the SOI layer measured in step (d) such that thickness of the SOI layer is adjusted to be the target value after etching, and removing the thermal oxide film formed in step (a) before or after step (b).

Abstract: A burn-in test process is omitted for some or all lots. In burn-in necessity determination processing, whether each semiconductor chip requires a burn-in test to be performed is determined based on measurement data obtained in a probe test process. In an assembly process, based on the results of determination made in the burn-in necessity determination processing, the assembled packages are sorted into a first lot which includes packages each including a semiconductor chip determined to require a burn-in test to be performed and a second lot which includes packages each including a semiconductor chip determined to require no burn-in test to be performed. In a burn-in test process, only the packages of the first lot are subjected to a burn-in test.

Abstract: In embodiments, a high voltage semiconductor device includes a gate structure disposed on a substrate, a source region disposed at a surface portion of the substrate adjacent to one side of the gate structure, a drift region disposed at a surface portion of the substrate adjacent to another side of the gate structure, a drain region disposed at a surface portion of the drift region spaced from the gate structure, and an electrode structure disposed on the drift region to generate a vertical electric field between the gate structure and the drain region.

Abstract: Various embodiments are directed toward a circuit configured to act as a Josephson junction. The circuit includes: a junction stack on a substrate, the junction stack including a portion of a first superconductor electrode, with an interface layer on a top side of the first superconductor electrode and configured to act as a tunneling barrier for the junction stack. The circuit may also comprise a first portion of a second superconductor electrode on top of the interface layer. A spacer may separate the portion of the first superconductor electrode in the junction stack from a second portion of the second superconductor electrode outside the junction stack where the second superconductor electrode overlays the first superconductor electrode.

Abstract: A method for fabricating a photonic composite device for splitting functionality across materials comprises providing a composite device having a platform and a chip bonded in the platform. The chip is processed comprising patterning, etching, deposition, and/or other processing steps while the chip is bonded to the platform. The chip is used as a gain medium and the platform is at least partially made of silicon.

Abstract: A device includes a semiconductor region in a semiconductor chip, a gate dielectric layer over the semiconductor region, and a gate electrode over the gate dielectric. A drain region is disposed at a top surface of the semiconductor region and adjacent to the gate electrode. A gate spacer is on a sidewall of the gate electrode. A dielectric layer is disposed over the gate electrode and the gate spacer. A conductive field plate is over the dielectric layer, wherein the conductive field plate has a portion on a drain side of the gate electrode. A conductive via is disposed in the semiconductor region. A source electrode is underlying the semiconductor region, wherein the source electrode is electrically shorted to the conductive field plate through the conductive via.

Abstract: Disclosed are a method for eliminating self-magnetization of a mask, a method for manufacturing a substrate and a mask testing device. The mask may include a plurality of metal stripes spaced from each other. The method may include a step of: energizing the mask, so as to enable the plurality of metal stripes to carry like charges, thereby separating every metal stripe from other adjacent metal stripes bonded together.

Abstract: An apparatus includes a channel layer, a first layer, a hole barrier layer and a second layer. The channel layer may be configured to carry a drain current in response to a voltage at a gate node. The first layer may be between the channel layer and the gate node. The first layer generally has a first bandgap. The hole barrier layer may be in contact with the first layer. The hole barrier layer generally has a second bandgap that (i) forms a valence band offset relative to the first bandgap and (ii) is configured to impede holes generated in one or more of the channel layer and the first layer from reaching the gate node. The gate node may be in contact with the second layer. The apparatus generally forms a field effect transistor.

Abstract: Provided is a super junction semiconductor device. The super junction semiconductor device includes a vertical pillar region located in an active region and horizontal pillar regions located in a termination region that are connected with each other while simultaneously not floating the entire pillar region in the termination region. Thus, a charge compensation difference, generated among pillar regions, is caused to be offset, although the length of the termination region is relatively short.

Abstract: A method includes aligning a top package to a bottom package using an alignment mark in the bottom package, and placing the top package over the bottom package, wherein the top package is aligned to the bottom package after the placing the top package over the bottom package. A reflow is then performed to bond the top package to the bottom package.

Abstract: To provide a light-emitting device or an input/output device with little unevenness in display luminance or high reliability and to provide an input/output device with high detection sensitivity, a light-emitting device is configured to include a first substrate, a light-emitting element over the first substrate, a first conductive layer over the light-emitting element, a first insulating layer over the first conductive layer, a second conductive layer over the first insulating layer, and a second substrate over the second conductive layer. The light-emitting element includes a first electrode over the first substrate, a layer containing a light-emitting organic compound over the first electrode, and a second electrode over the layer containing a light-emitting organic compound. The second electrode is electrically connected to the first and second conductive layers. The first conductive layer and the second electrode transmit light emitted from the light-emitting element.