Abstract: A device includes a semiconductor substrate having a first conductivity type, a device isolating region in the semiconductor substrate, defining an active area, and having a second conductivity type, a body region in the active area and having the first conductivity type, and a drain region in the active area and spaced from the body region to define a conduction path of the device, the drain region having the second conductivity type. The device isolating region and the body region are spaced from one another to establish a first breakdown voltage lower than a second breakdown voltage in the conduction path.

Abstract: The invention relates to a method for encapsulating an electronic arrangement against permeants, wherein an electronic arrangement is made available on a substrate, wherein, in a vacuum, that area of the substrate which embraces that region of the electronic arrangement which is to be encapsulated, preferably said area and that region of the electronic arrangement which is to be encapsulated, is brought into contact with a sheet material comprising at least one adhesive compound and a composite is produced therefrom. The invention also relates to an apparatus for implementing the method and to an encapsulated electronic arrangement produced thereby.

Abstract: A high electron mobility transistor (HEMT) according to example embodiments includes a channel layer, a channel supply layer on the channel layer, a source electrode and a drain electrode on at least one of the channel layer and the channel supply layer, a gate electrode between the source electrode and the drain electrode, and a Schottky electrode forming a Schottky contact with the channel supply layer. An upper surface of the channel supply layer may define a Schottky electrode accommodation unit. At least part of the Schottky electrode may be in the Schottky electrode accommodation unit. The Schottky electrode is electrically connected to the source electrode.

Abstract: A thermal isolation layer is formed between the bit line (BL) layers or word line (WL) layers of the decks of a multi-deck phase-change cross-point memory to mitigate thermal problem disturb of memory cells that tends to increase as memory sizes are scaled smaller. Embodiments of the subject matter disclosed herein are suitable for, but are not limited to, solid-state memory arrays and solid-state drives.

Abstract: A method to form a titanium nitride (TiN) hard mask in the Damascene process of forming interconnects during the fabrication of a semiconductor device, while the type and magnitude of stress carried by the TiN hard mask is controlled. The TiN hard mask is formed in a multi-layered structure where each sub-layer is formed successively by repeating a cycle of processes comprising TiN and chlorine PECVD deposition, and N2/H2 plasma gas treatment. During its formation, the stress to be carried by the TiN hard mask is controlled by controlling the number of TiN sub-layers and the plasma gas treatment duration such that the stress may counter-balance predetermined external stress anticipated on a conventionally made TiN hard mask, which causes trench sidewall distortion, trench opening shrinkage, and gap filling problem.

Abstract: Electronic modules, and methods of forming and operating modules, are described. The modules include a capacitor, a first switching device, and a second switching device. The electronic modules further include a substrate such as a DBC substrate, which includes an insulating layer between a first metal layer and a second metal layer, and may include multiple layers of DBC substrates stacked over one another. The first metal layer includes a first portion and a second portion isolated from one another by a trench formed through the first metal layer between the two portions. The first and second switching devices are over the first metal layer, a first terminal of the capacitor is electrically connected to the first portion of the first metal layer, and a second terminal of the capacitor is electrically connected to the second portion of the first metal layer, with the capacitor extending over the trench.

Abstract: Methodologies enabling integration of optical components in ICs and a resulting device are disclosed. Embodiments include: providing a first substrate layer of an IC separated from a second substrate level by an insulator layer; providing a transistor on the second substrate layer; and providing an optical component on the first substrate layer, the optical component being connected to the transistor.

Abstract: A lensfree imaging and sensing device includes an image sensor comprising an array of pixels and a substantially optically transparent layer disposed above the image sensor. Nano-sized features that support surface plasmon waves are populated on the substantially optically transparent layer separating the image sensor from the nano-sized features. The nano-sized features may include apertures through a substantially optically opaque layer (e.g., metal layer) or they may include antennas. An illumination source is provided that is configured to illuminate a sample. At least one processor is operatively coupled to the image sensor. Changes to the detected transmission pattern at the image sensor are used to sense conditions at or near the surface containing the nano-sized features. Conditions may include binding events or other changes to the index of refraction occurring near the surface of the device.

Abstract: A super junction semiconductor device may include one or more doped zones in a cell area. A drift layer is provided between a doped layer of a first conductivity type and the one or more doped zones. The drift layer includes first regions of the first conductivity type and second regions of a second conductivity type, which is the opposite of the first conductivity type. In an edge area that surrounds the cell area, the first regions may include first portions separating the second regions in a first direction and second portions separating the second regions in a second direction orthogonal to the first direction. The first and second portions are arranged such that a longest second region in the edge area is at most half as long as a dimension of the edge area parallel to the longest second region.

Abstract: This description relates to a method of making a semiconductor device including forming an inter-level dielectric (ILD) layer over a substrate and forming a layer set over the ILD layer. The method further includes etching the layer set to form a tapered opening in the layer set and etching the ILD layer using the layer set as a mask to form an opening in the ILD layer. The opening in the ILD layer has a line width roughness (LWR) of less than 3 nanometers (nm). This description also relates to a semiconductor device including an inter-level dielectric (ILD) layer over a substrate; and a layer set over the ILD layer. The layer set has a tapered opening within the layer set. Etching the layer set comprises forming the tapered opening having sidewalls at an angle with respect to a top surface of the ILD layer ranging from 85-degrees to 90-degrees.

Abstract: A vertical memory device and a method of fabricating the same are provided. The vertical type semiconductor device includes a common source region formed in a cell area of a semiconductor substrate. A channel region is formed on the common source region. The channel region has a predetermined height and a first diameter. A drain region is formed on the channel region. The drain region has a predetermined height and a second diameter larger than the first diameter. A first gate electrode surrounding the channel region.

Abstract: A mechanism for forming a semiconductor device is described. The semiconductor device includes a substrate and an inter-layer dielectric (ILD) layer over the substrate. The intermediate semiconductor device further includes a first layer set over the ILD layer and a second layer set over the first layer set. The intermediate semiconductor device further includes a photoresist layer over the second layer set. The method further includes etching the second layer set to form a tapered opening in the second layer set, the tapered opening having sidewalls at an angle with respect to a top surface of the ILD layer ranging from about 85-degrees to about 90-degrees, but less than 90-degrees. The method further includes etching the first layer set to form an opening in the first layer set and etching the ILD layer using the first layer set as a mask to form an opening in the ILD layer.

Abstract: In some embodiments, Cu—In—Ga precursor films are deposited by co-sputtering from multiple targets. Specifically, the co-sputtering method is used to form layers that include In. The co-sputtering reduces the tendency for the In component to agglomerate and results in smoother, more uniform films. In some embodiments, the Ga concentration in one or more target(s) is between about 25 atomic % and about 66 atomic %. The deposition may be performed in a batch or in-line deposition system. If an in-line deposition system is used, the movement of the substrates through the system may be continuous or may follow a “stop and soak” method of substrate transport.

Abstract: Embodiments of the present disclosure describe semiconductor substrate techniques and configurations for an optical receiver. In one embodiment, a system includes a semiconductor substrate having one or more optical alignment features formed in a surface of the semiconductor substrate and an optical receiver assembly coupled with the semiconductor substrate, the optical receiver assembly including a photodetector device coupled with the surface of the semiconductor substrate, wherein the one or more optical alignment features facilitate precise optical alignment between a lens assembly and the photodetector device when the lens assembly is coupled with the semiconductor substrate using the one or more optical alignment features. Other embodiments may be described and/or claimed.

Abstract: A method for crystallizing a silicon substrate includes manufacturing a crystallized silicon test substrate that is crystallized by scanning excimer laser annealing beams with different energy densities on respective areas of an amorphous silicon test substrate, irradiating a surface of the crystallized silicon test substrate using a light source, and measuring reflectivity corresponding to the respective areas of the crystallized silicon test substrate in a visible light wavelength range, extracting average reflectivities of the respective areas of the crystallized silicon test substrate in wavelength ranges corresponding to respective colors, calculating an optimum energy density (OPED) index per energy density by using a value acquired by subtracting average reflectivity of red-based colors from average reflectivity of blue-based colors, selecting an optimal energy density, and crystallizing an amorphous silicon substrate using the optimal energy density.

Abstract: Described herein are systems and methods method for forming semiconductor films. In some embodiment, the methods comprising depositing the source solution containing a solvent and plurality of types of metal ionic species and a second type on a substrate heated to a temperature at or above the boiling point of the solvent. In some embodiments, methods and apparatus for exposing a substrate to a gas are also provided.

Abstract: A method includes forming top metal lines over a semiconductor substrate, wherein the semiconductor substrate is a portion of a wafer having a bevel. When the top metal lines are exposed, an etchant is supplied on the bevel, wherein regions of the wafer sprayed with the etchant has an inner defining line forming a first ring having a first diameter. A trimming step is performed to trim an edge portion of the wafer, wherein an edge of a remaining portion of the wafer has a second diameter substantially equal to or smaller than the first diameter.

Abstract: A method for processing a silicon wafer is provided. The method includes allowing an etchant to flow along a surface of the silicon wafer to form a line in which a plurality of apertures are arranged in a flow direction of the etchant from an upstream side to a downstream side. The apertures arranged in the line include a first aperture formed on the most upstream side and a second aperture formed downstream of the first aperture in the flow direction of the etchant. The first aperture and the second aperture are subjected to different processes after being formed.

Abstract: An integrated circuit includes a semiconductor substrate, a silicon layer, a buried isolating layer arranged between the substrate and the layer, a bipolar transistor comprising a collector and emitter having a first doping, and a base and a base contact having a second doping, the base forming a junction with the collector and emitter, the collector, emitter, base contact, and the base being coplanar, a well having the second doping and plumb with the collector, emitter, base contact and base, the well separating the collector, emitter and base contact from the substrate, having the second doping and extending between the base contact and base, a isolating trench plumb with the base and extending beyond the layer but without reaching a bottom of the emitter and collector, and another isolating trench arranged between the base contact, collector, and emitter, the trench extending beyond the buried layer into the well.

Abstract: A resistive memory device and a method for fabricating the resistive memory device. The memory device includes a first electrode and a resistive memory element in electrical contact. The memory device also includes a non-programmable stabilizer element in electrical and thermal contact with the resistive memory element. The stabilizer element has at least one physical dimension based on a physical characteristic of the resistive memory element such that the maximum resistance of the stabilizer element is substantially less than the maximum resistance of the resistive memory element.