Abstract: A semiconductor device provides an element arrangement region on a semiconductor substrate including: a first semiconductor region on the semiconductor substrate; a second semiconductor region on the first semiconductor region; multiple trench gates penetrating the first semiconductor region and reaching the second semiconductor region; a third semiconductor region contacting the trench gate; a fourth semiconductor region on a rear surface; a first electrode connected to the first and second semiconductor regions; and a second electrode connected to the fourth semiconductor region. Each trench gate includes a main trench gate for generating a channel and a dummy trench gate for improving a withstand voltage of a component. The device further includes: a dummy gate wiring for applying a predetermined voltage to the dummy trench gate; and a dummy pad connected to the dummy gate wiring. The dummy pad and the first electrode are connected by a conductive member.

Abstract: A semiconductor apparatus includes gate electrodes and interlayer insulating layers alternately stacked on a substrate, channel regions penetrating through the gate electrodes and the interlayer insulating layers, a conductive layer extending from an uppermost layer among the interlayer insulating layers to the substrate by penetrating through the gate electrodes and the interlayer insulating layers between the channel regions, and having an uneven pattern on an outer side wall thereof, a spacer layer disposed on the outer side wall, and a barrier layer disposed on at least one side surface of the spacer layer, wherein the spacer layer and the barrier layer have different etch selectivities.

Abstract: Electronic modules, and methods of forming and operating modules, are described. The modules include a capacitor, a first switching device, and a second switching device. The electronic modules further include a substrate such as a DBC substrate, which includes an insulating layer between a first metal layer and a second metal layer, and may include multiple layers of DBC substrates stacked over one another. The first metal layer includes a first portion and a second portion isolated from one another by a trench formed through the first metal layer between the two portions. The first and second switching devices are over the first metal layer, a first terminal of the capacitor is electrically connected to the first portion of the first metal layer, and a second terminal of the capacitor is electrically connected to the second portion of the first metal layer, with the capacitor extending over the trench.

Abstract: A device includes a semiconductor substrate having a first conductivity type, a device isolating region in the semiconductor substrate, defining an active area, and having a second conductivity type, a body region in the active area and having the first conductivity type, and a drain region in the active area and spaced from the body region to define a conduction path of the device, the drain region having the second conductivity type. At least one of the body region and the device isolating region includes a plurality of peripheral, constituent regions disposed along a lateral periphery of the active area, each peripheral, constituent region defining a non-uniform spacing between the device isolating region and the body region. The non-uniform spacing at a respective peripheral region of the plurality of peripheral, constituent regions establishes a first breakdown voltage lower than a second breakdown voltage in the conduction path.

Abstract: A chip includes a semiconductor substrate, and a first N-type Metal Oxide Semiconductor Field Effect Transistor (NMOSFET) at a surface of the semiconductor substrate. The first NMOSFET includes a gate stack over the semiconductor substrate, a source/drain region adjacent to the gate stack, and a dislocation plane having a portion in the source/drain region. The chip further includes a second NMOSFET at the surface of the semiconductor substrate, wherein the second NMOSFET is free from dislocation planes.

Abstract: In a semiconductor device, a p+ back gate region (PBG) is arranged in a main surface (S1) between first and second portions (P1, P2) of an n+ source region (SR), and arranged on a side closer to an n+ drain region (DR) with respect to the n+ source region (SR). Thereby, a semiconductor device having a high on-state breakdown voltage can be obtained.

Abstract: Methods of fabricating semiconductor devices, such as monolithic three-dimensional NAND memory string devices, include selectively forming semiconductor material charge storage regions over first material layers exposed on a sidewall of a front side opening extending through a stack comprising an alternating plurality of first and second material layers using a difference in incubation time for the semiconductor material on the first material relative to an incubation time for the semiconductor material on the second material of the stack. In other embodiments, a silicon layer is selectively deposited on silicon nitride on a surface having at least one first portion including silicon oxide and at least one second portion including silicon nitride using a difference in an incubation time for the silicon on silicon nitride relative to an incubation time for the silicon on silicon oxide.

Abstract: According to an embodiment, a nonvolatile semiconductor memory device comprises a plurality of conductive layers stacked in a first direction via an inter-layer insulating layer. In addition, the nonvolatile semiconductor memory device comprises: a semiconductor layer having the first direction as a longer direction; a tunnel insulating layer contacting a side surface of the semiconductor layer; a charge accumulation layer contacting a side surface of the tunnel insulating layer; and a block insulating layer contacting a portion facing the conductive layer, of a side surface of the charge accumulation layer. Moreover, the portion facing the conductive layer, of the charge accumulation layer is thinner compared to a portion facing the inter-layer insulating layer, of the charge accumulation layer.

Abstract: Methods of forming doped elements of semiconductor device structures include forming trenches having undercut portions separating stem portions of a substrate. The stem portions extend between a base portion of the substrate and overlying broader portions of the substrate material. A carrier material including a dopant is formed at least on the sides of the stems in the undercut portions of the trenches. The dopant is diffused from the carrier material into the stems. As such, the narrow stem portions of the substrate become doped with a targeted dopant-delivery method. The doped stems may form or be incorporated within buried, doped, conductive elements of semiconductor device structures, such as digit lines of memory arrays. Also disclosed are related semiconductor device structures.

Abstract: A method of making N-type semiconductor layer includes following steps. A semiconductor carbon nanotube layer is provided. A hafnium oxide layer is deposited on the semiconductor carbon nanotube layer via atomic layer deposition, wherein the atomic layer deposition includes following substeps. The semiconductor carbon nanotube layer is located into an atomic layer deposition system. The semiconductor carbon nanotube layer is heated to a temperature ranging from about 140° C. to about 200° C. A protective gas is continuously introduced into the atomic layer deposition system. The hafnium oxide layer is formed on the semiconductor carbon nanotube layer via introducing hafnium source and water vapor one by one into the atomic layer deposition system in a pulse manner.

Abstract: A method of manufacturing an organic light emitting display includes forming a first light-emitting layer on a substrate, forming a first portion of a second light-emitting layer on the first light-emitting layer, forming a third light-emitting layer on the first light-emitting layer, and forming a second portion of the second light-emitting layer on the first portion of the second light-emitting layer.

Abstract: A light emitting device and a method of fabricating the same is provided. The device includes an LED chip having a first main surface, a second main surface opposing the first main surface, and one or more side surfaces extending between the first and second main surfaces. A reflective side layer surrounds the one or more side surfaces of the LED chip. The reflective side layer has a first main surface and a second main surface opposing the first main surface extending in a first direction, and an opening extending between the first and second main surfaces in a second direction substantially perpendicular to the first direction. The opening surrounds the chip. A phosphor film overlies the first main surface of the chip and the first main surface of the reflective side layer. At least one electrode is disposed on the second main surface of the chip.

Abstract: A resin package includes a molded resin housing, a first lead, and a second lead. The molded resin housing includes a cavity open upward. The cavity includes an inner surface. The inner surface includes a curved portion and a stepped portion provided on a lower side of the curved portion. The first lead and the second lead are provided in a bottom portion of the cavity such that at least a part of the first lead and the second lead is exposed from the molded resin housing. The first lead includes an elevated portion on which a light emitting element is mounted. An upper surface of the elevated portion is provided higher than an upper end portion of the stepped portion.

Abstract: An electronic device includes an electronic element, and a wire bonded to the electronic element. The electronic element includes a bonding pad to which the wire is bonded. The main component of the bonding pad is Al. A metal is mixed in the wire, and the mixed metal is one of Pt, Pd and Au.

Abstract: An optoelectronic component includes a layer structure which has a first gallium nitride layer and an aluminum-containing nitride intermediate layer. In this case, the aluminum-containing nitride intermediate layer adjoins the first gallium nitride layer. The layer structure has an undoped second gallium nitride layer which adjoins the aluminum-containing nitride intermediate layer.

Abstract: A package includes a first package component, a second package component over the first package component, and a solder region bonding the first package component to the second package component. At least one ball-height control stud separates the first package component and the second package component from each other, and defines a standoff distance between the first package component and the second package component.

Abstract: Described are techniques related to semiconductor devices that make use of encapsulant. In one implementation, a semiconductor device may be manufactured to include at least an encapsulant that includes at least glass particles.

Abstract: A plurality of gate structures are formed straddling nFET semiconductor fins and pFET semiconductor fins which extend upwards from a surface of a semiconductor substrate. A boron-doped silicon germanium alloy material is epitaxially grown from exposed surfaces of both the nFET semiconductor fins and the pFET semiconductor fins not protected by the gate structures. An anneal is then performed. During the anneal, silicon and germanium from the boron-doped silicon germanium alloy material diffuse into the nFET semiconductor fins and act as an n-type dopant forming a junction in the nFET semiconductor fins. Since boron is a Group IIIA element it does not have any adverse effect. During the same anneal, boron from the boron-doped silicon germanium alloy material will diffuse into the pFET semiconductor fins to form a junction therein.

Abstract: The invention provides a display motherboard, a display panel and a display device for solving the problem of unsmooth cutting of the display motherboard in the prior art during cutting. In the display motherboard, the display panel and the display device provided by the present invention, a cutting area of the display motherboard is provided with a raised portion on one side close to sealant, and the raised portion can make the cutting stress more concentrated when the display motherboard is cut, so that adhesion of the sealant to substrates is reduced and thus the display motherboard is cut more smoothly.

Abstract: An integrated circuit includes a transistor, an UTBOX buried insulating layer disposed under it and a ground plane disposed under the layer. A well is disposed under the plane and a first trench is at the periphery of the transistor and extends through the layer into the well. There is a substrate under the well and a p-n diode on a side of the transistor. The diode comprises first and second zones of opposite doping and the first zone is configured for electrical connection to a first electrode of the transistor. The first and second zones are coplanar with the plane and a second trench for separating the first and second zones. The second trench extends through the layer into the plane to a depth less than an interface between the plane and the well. There is a third zone under the second trench forming a junction between the zones.