Patents Examined by Viet Q. Nguyen
  • Patent number: 11367205
    Abstract: Dense feature scale detection can be implemented using multiple convolutional neural networks trained on scale data to more accurately and efficiently match pixels between images. An input image can be used to generate multiple scaled images. The multiple scaled images are input into a feature net, which outputs feature data for the multiple scaled images. An attention net is used to generate an attention map from the input image. The attention map assigns emphasis as a soft distribution to different scales based on texture analysis. The feature data and the attention data can be combined through a multiplication process and then summed to generate dense features for comparison.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: June 21, 2022
    Assignee: Snap Inc.
    Inventors: Shenlong Wang, Linjie Luo, Ning Zhang, Jia Li
  • Patent number: 11367478
    Abstract: The embodiments provide an integrated circuit structure and a memory, and relates to the field of semiconductor memory technologies. The integrated circuit structure includes: a pad region, including a plurality of signal pads arranged along a target direction; and a circuit region arranged on one side of the pad region. The circuit region includes a plurality of input/output circuit modules arranged along the target direction and correspondingly connected to the signal pads. Each of the input/output circuit modules is configured to implement a sampling operation of an input signal and write a sampling result into a storage array, and read data stored in the storage array. A size of the circuit region along the target direction is smaller than that of the pad region along the target direction. According to the present disclosure, the performance of a write operation can be improved for the memory.
    Type: Grant
    Filed: March 10, 2021
    Date of Patent: June 21, 2022
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Liang Zhang
  • Patent number: 11361547
    Abstract: An object detection apparatus comprising: an input part configured to input video data, an extraction part configured to extract image data from the video data, and a determination part configured to determine whether or not the image data includes an object, wherein the determination part is configured to: set a plurality of regions in a learning image data such that the object appearing in the learning image data extracted from a learning video data captured in advance extends over at least the plurality of regions, assign a learning teach label to each of the regions set, and determine whether or not the image data includes the object by using a prediction model generated by utilizing the learning teach label assigned to each of the regions set.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: June 14, 2022
    Assignee: NEC COMMUNICATION SYSTEMS, LTD.
    Inventors: Noriyuki Aoki, Masanori Takaoka, Tetsuya Ito, Hiroki Yokota
  • Patent number: 11355177
    Abstract: A memory device includes: a first memory cell mat that includes first multi-layer level sub word lines positioned over a substrate; a second memory cell mat that is laterally spaced apart from the first memory cell mat and includes second multi-layer level sub word lines; a first sub word line driver circuit that is positioned underneath the first memory cell mat; and a second sub word line driver circuit that is positioned underneath the second memory cell mat, wherein the first sub word line driver circuit is positioned underneath ends of the first multi-layer level sub word lines, and the second sub word line driver circuit is positioned underneath ends of the second multi-layer level sub word lines.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: June 7, 2022
    Assignee: SK hynix Inc.
    Inventors: Seung-Hwan Kim, Su-Ock Chung, Seon-Yong Cha
  • Patent number: 11355181
    Abstract: A high bandwidth memory and a system having the same are disclosed. The high bandwidth memory includes a buffer die and a plurality of memory dies, each of which includes at least one first processing element bank group and at least one second processing element bank group. The at least one first processing element bank group includes one or more first banks connected to one or more first bank input/output line groups, and a first processing element controller connected to the one or more first bank input/output line groups and a first global input/output line group, and is configured to perform a first processing operation on first data output from one of the one or more first bank input/output line groups and second data transmitted through the first global input/output line group based on a first instruction that is generated based on a first processing command.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: June 7, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seongil O, Namsung Kim, Sukhan Lee
  • Patent number: 11350135
    Abstract: A method and apparatus for sample adaptive offset without sign coding. The method includes selecting an edge offset type for at least a portion of an image, classifying at least one pixel of at least the portion of the image into edge shape category, calculating an offset of the pixel, determining the offset is larger or smaller than a predetermined threshold, changing a sign of the offset based on the threshold determination; and performing entropy coding accounting for the sign of the offset and the value of the offset.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: May 31, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Woo-Shik Kim, Do-Kyoung Kwon
  • Patent number: 11348924
    Abstract: A semiconductor memory device may include a bit line extending in a first direction, a first conductive pattern extending in a second direction intersecting the first direction, a semiconductor pattern connecting the bit line and the first conductive pattern, a second conductive pattern including an insertion portion in the first conductive pattern, and a dielectric layer between the first conductive pattern and the second conductive pattern. The insertion portion of the second conductive pattern may have a width which increases as a distance from the semiconductor pattern increases.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: May 31, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae Hoon Kim, Kwang-Ho Park, Yong-Hoon Son, Hyunji Song, Gyeonghee Lee, Seungjae Jung
  • Patent number: 11348923
    Abstract: Multi-port semiconductor memory cells including a common floating body region configured to be charged to a level indicative of a memory state of the memory cell. The multi-port semiconductor memory cells include a plurality of gates and conductive regions interfacing with said floating body region. Arrays of memory cells and method of operating said memory arrays are disclosed for making a memory device.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: May 31, 2022
    Assignee: Zeno Semiconductor, Inc.
    Inventor: Yuniarto Widjaja
  • Patent number: 11341741
    Abstract: A method for controlling an unmanned aerial vehicle (UAV) to track a monitored person is provided. The method includes directing the UAV toward a target location the target location being based on past or present location information provided by a personal monitoring device attached to a monitored person, the location information representing the location of the personal monitoring device; assuming with the UAV a surveillance position relative to the target location; and determining that the monitored device is proximate to the target location by receiving signals from the personal monitoring device and/or observing the monitored person through a camera on the UAV.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: May 24, 2022
    Assignee: Satellite Tracking of People LLC
    Inventor: David W. LeJeune, Jr.
  • Patent number: 11342906
    Abstract: Devices for generating a delay output signal are disclosed. A device may include a first delay circuit and a second delay circuit coupled in series between a first node and a second node in a delay path for the device, and having a third node therebetween. The device may also include a third circuit coupled to the third node and configured to charge the third node responsive to detecting a signal has passed through the first node and the third node. Associated semiconductor devices and methods are also disclosed.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: May 24, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Hiroshi Akamatsu, Zhi Qi Huang
  • Patent number: 11335408
    Abstract: A counter can have a number of sensing components. Each respective sensing component can be configured to sense a respective event and can include a respective first capacitor configured to be selectively coupled to a second capacitor in response to the respective sensing component sensing the respective event. The second capacitor can be configured to be charged to a voltage by each respective first capacitor that is selectively coupled to the second capacitor. The counter can have a comparator with a first input coupled to the second capacitor and a second input coupled to a reference voltage corresponding to a threshold quantity of events. The comparator can be configured to output a signal indicative of the threshold quantity of events being sensed in response to the voltage of the second capacitor being greater than or equal to the reference voltage.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: May 17, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Marco Sforzin, Umberto Di Vincenzo
  • Patent number: 11328406
    Abstract: A computer-implemented method for assessing material microstructure of a machine component involves obtaining a raw image of a section of the component captured via a microscope. The method further includes pre-processing the raw image to generate a ternary image defined by pixel data including three levels of intensities. The method further includes identifying, from the ternary image, phase boundaries delineating at a phase in a primary constituent material of the component. The method further includes determining a volume associated with the phase based on the identified phase boundaries. The proposed method may be utilized, for example, as an automated tool for assessing material degradation and for quality control of gas turbine engine components.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: May 10, 2022
    Assignee: Siemens Aktiengesellschaft
    Inventors: Arindam Dasgupta, Biswadip Dey, Anand A. Kulkarni, Amit Chakraborty
  • Patent number: 11326955
    Abstract: The present invention relates to an intelligent flame detection apparatus and method using an infrared thermogram, which combine a conventional flame detector with an infrared thermographic camera and an infrared thermogram processing technology, and which enable whether a flame signal received from a flame sensor is an allowed flame or an artificial flame to be accurately detected, thereby improving the accuracy of fire alarms.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: May 10, 2022
    Assignee: HANSUN ST(SECURITY TECHNOLOGY) INC.
    Inventor: Suun Kim
  • Patent number: 11322211
    Abstract: Memory devices might include a controller for access of an array of memory cells and a differential storage device comprising a pair of gate-connected non-volatile memory cells, wherein the controller is configured to cause the memory device to obtain information indicative of a data value stored in a particular memory cell of the array of memory cells, program additional data to the particular memory cell, determine if a power loss to the memory device is indicated while programming the additional data to the particular memory cell, and, if a power loss to the memory device is indicated, selectively program one memory cell of the pair of gate-connected non-volatile memory cells responsive to the information indicative of the data value stored in the particular memory cell.
    Type: Grant
    Filed: April 14, 2021
    Date of Patent: May 3, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Rainer Bonitz
  • Patent number: 11321830
    Abstract: An image detection method includes determining, by a terminal in a skin detection mode, a to-be-detected original image in a raw format based on a to-be-detected feature, processing the to-be-detected original image according to a preset rule corresponding to the to-be-detected feature to obtain a detection-specific image, determining a normal image that is in a Joint Photographic Experts Group (JPEG) format, detecting the detection-specific image to determine a detection result image, and determining a to-be-displayed image based on the detection result image and the normal image.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: May 3, 2022
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Xin Ding, Chen Dong, Henghui Lu
  • Patent number: 11323704
    Abstract: The present invention relates to an apparatus and method for encoding and decoding an image by skip encoding. The image-encoding method by skip encoding, which performs intra-prediction, comprises: performing a filtering operation on the signal which is reconstructed prior to an encoding object signal in an encoding object image; using the filtered reconstructed signal to generate a prediction signal for the encoding object signal; setting the generated prediction signal as a reconstruction signal for the encoding object signal; and not encoding the residual signal which can be generated on the basis of the difference between the encoding object signal and the prediction signal, thereby performing skip encoding on the encoding object signal.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: May 3, 2022
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung Chang Lim, Ha Hyun Lee, Se Yoon Jeong, Hui Yong Kim, Suk Hee Cho, Jong Ho Kim, Jin Ho Lee, Jin Soo Choi, Jin Woong Kim, Chie Teuk Ahn, Dong Gyu Sim, Seoung Jun Oh, Gwang Hoon Park, Sea Nae Park, Chan Woong Jeon
  • Patent number: 11316024
    Abstract: A memory device, and method of making the same, that includes a substrate of semiconductor material of a first conductivity type, first and second regions spaced apart in the substrate and having a second conductivity type different than the first conductivity type, with a first channel region in the substrate extending between the first and second regions, a first floating gate disposed over and insulated from a first portion of the first channel region adjacent to the second region, a first coupling gate disposed over and insulated from the first floating gate, a first word line gate disposed over and insulated from a second portion of the first channel region adjacent the first region, and a first erase gate disposed over and insulated from the first word line gate.
    Type: Grant
    Filed: February 2, 2021
    Date of Patent: April 26, 2022
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Chunming Wang, Xian Liu, Guo Xiang Song, Leo Xing, Nhan Do
  • Patent number: 11317510
    Abstract: The embodiments described herein describe technologies for memory systems. One implementation of a memory system includes a motherboard substrate with multiple module sockets, at least one of which is populated with a memory module. A first set of data lines is disposed on the motherboard substrate and coupled to the module sockets. The first set of data lines includes a first subset of point-to-point data lines coupled between a memory controller and a first socket and a second subset of point-to-point data lines coupled between the memory controller and a second socket. A second set of data lines is disposed on the motherboard substrate and coupled between the first socket and the second socket. The first and second sets of data lines can make up a memory channel.
    Type: Grant
    Filed: October 16, 2020
    Date of Patent: April 26, 2022
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Suresh Rajan
  • Patent number: 11309019
    Abstract: A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3). A control circuit controls the potentials of the word line and bit line according to input data and writes data into a memory cell. The control circuit writes data into the memory cell to a k-valued threshold voltage (k<=n) in a write operation, precharges the bit line once, and then changes the potential of the word line an i number of times to verify whether the memory cell has reached an i-valued (i<=k) threshold voltage.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: April 19, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Noboru Shibata, Tomoharu Tanaka
  • Patent number: 11302379
    Abstract: A semiconductor apparatus according to an embodiment of the present invention includes: a plurality of semiconductor chips that are laminated; a plurality of penetration electrodes that penetrate in a lamination direction through the plurality of semiconductor chips and that electrically connect together the plurality of semiconductor chips; and a plurality of input/output elements that are configured to perform a signal input/output operation to the plurality of penetration electrodes, wherein the semiconductor chips are joined together via no bump, one of the plurality of input/output elements is connected to each of the plurality of penetration electrodes such that a functional element connected to each of the plurality of penetration electrodes performs an ON or OFF operation at a predetermined timing, and the input/output element connected to a first of two adjacent penetration electrodes among the plurality of penetration electrodes and the input/output element connected to a second of two adjacent pene
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: April 12, 2022
    Assignees: HONDA MOTOR CO., LTD., TOKYO INSTITUTE OF TECHNOLOGY
    Inventors: Koji Sakui, Takayuki Ohba