Abstract: A complementary storage unit and a method of preparing the same, and a complementary memory. The complementary storage unit includes: a control transistor, a pull-up diode and a pull-down diode. The control transistor is configured to control reading and writing of the storage unit. One end of the pull-up diode is connected to a positive selection line, and the other end thereof is connected to a source end of the control transistor, so as to control a high-level input. One end of the pull-down diode is connected to a negative selection line, and the other end thereof is connected to the source end of the control transistor, so as to control a low-level input. The pull-up diode and the pull-down diode are symmetrically arranged in a first direction.

Abstract: A memory core characteristic screening method includes the following steps. A command signal transmitting step includes configuring a processing module to transmit a command signal to a memory device. A first internal operating step includes configuring the memory device to operate a first operation to one of a word line, a bit line pair and a column line after a first strobe signal delay time according to a first command. A second internal operating step includes configuring the memory device to operate a second operation to another one of the word line, the bit line pair and the column line after a second strobe signal delay time according to a second command. A memory core characteristic screening step includes screening a memory core characteristic by shorting a timing between the first strobe signal delay time and the second strobe signal delay time.

Abstract: A memory device having long data retention time and high reliability is provided. The memory device includes a driver circuit and a plurality of memory cells, the memory cell includes a transistor and a capacitor, and the transistor includes a metal oxide in a channel formation region. The transistor includes a first gate and a second gate, and in a period during which the memory cell retains data, negative potentials are applied to the first gate and the second gate of the transistor.

Abstract: The present invention generally relates to the field of replicating or copying keys. More specifically, the present invention relates to creating a copy of a master key based on a captured image of the master key. The present invention identifies a set of target key information based on vehicle and or lock information as well as the image of the master key to provide for the cutting of a duplicate key blade copy to be delivered to a user or to another location. Additional key information may also be captured along with the image of the master key.

Abstract: The memory device of the disclosure includes a fuse voltage generator, a fuse storage and a logic circuit. The fuse voltage generator generates a fuse voltage in response to an enable signal having a first logic level, and stop generating the fuse voltage in response to the enable signal having a second logic level. The fuse storage storages a setting data of the memory device. The fuse storage outputs the setting data in response to the fuse voltage. The logic circuit generates the enable signal in response to at least two operating signals.

Abstract: Control logic in a memory device causes a programming pulse of a set of programming pulses to be applied to a wordline associated with a memory cell of a memory device, where the memory cell is to be programmed to a target voltage level representing a first programming level. At a first time, first data is caused to be stored in a cache, the first data indicating that a threshold voltage of a memory cell exceeds the target voltage level. At a second time, the cache is caused to be refreshed to store second data indicating that the threshold voltage of the memory cell is less than the target voltage level. In view of the second data, a level shifting operation associated with the memory cell is caused to be executed.

Abstract: A sense amplifier circuit architecture includes a first NMOS layout, a second NMOS layout, a first PMOS layout, a second PMOS layout, a first processing structure layout and a second processing structure layout. The first NMOS layout includes first N-type active layers and first gate layers discretely arranged on the first N-type active layers. The second NMOS layout includes second N-type active layers and second gate layers discretely arranged on the second N-type active layers. The first PMOS layout includes first P-type active layers and third gate layers discretely arranged on the first P-type active layers. The second PMOS layout includes second P-type active layers and fourth gate layers discretely arranged on the second P-type active layers. The first processing structure layout includes first active layers and a first isolation gate. The second processing structure layout includes second active layers and a second isolation gate.

Abstract: The present invention relates to a method of assisting in diagnosis of a target heart disease using a retinal image, the method including: obtaining a target retinal image which is obtained by imaging a retina of a testee; on the basis of the target retinal image, obtaining heart disease diagnosis assistance information of the testee according to the target retinal image, via a heart disease diagnosis assistance neural network model which obtains diagnosis assistance information that is used for diagnosis of the target heart disease according to the retinal image; and outputting the heart disease diagnosis assistance information of the testee.

Abstract: A memory structure of an integrated circuit includes a plurality of memory arrays arranged in parallel along the first direction and extending along the second direction, a sensitivity amplifier array extending along the second direction is arranged between every two memory arrays, and the sensitivity amplifier array includes an odd-numbered sensitivity amplifier array and an even-numbered sensitivity amplifier array, the odd-numbered sensitivity amplifier array is connected to an odd-numbered global signal line, and the even-numbered sensitivity amplifier array is connected to the even-numbered global signal line; a first sensitivity amplifier array is arranged between the memory arrays at the edge, and the first sensitivity amplifier array is connected to both the odd-numbered global signal line and the even-numbered global signal line. The present disclosure can improve reliability, yield and test success rate of the memory products.

Abstract: System and method for extracting human pose information from an image, comprising a feature extractor connected to a database, a convolutional neural network (CNN) with a plurality of CNN layers. Said system/method further comprising at least one of the following modules: a 2D body skeleton detector for determining 2D body skeleton information from the human-related image features; a body silhouette detector for determining body silhouette information from the human-related image features; a hand silhouette detector for determining hand silhouette detector from the human-related image features; a hand skeleton detector for determining hand skeleton from the human-related image features; a 3D body skeleton detector for determining 3D body skeleton from the human-related image features; and a facial keypoints detector for determining facial keypoints from the human-related image features.

Abstract: Embodiments of the present disclosure described herein relate to a computing in memory electronic device that supports current based analog operations and time based analog-to-digital conversion.

Abstract: In an embodiment, an apparatus an apparatus including a memory module is described. The memory module can include a plurality of memory ranks and a register clock driver (RCD) coupled to the plurality of memory ranks. The RCD can include a receiver configured to receive a chip select signal for selecting one or more memory ranks. The RCD can further include a logic circuit coupled to the receiver, and an output driver coupled to the logic circuit. The RCD can further include a loopback circuit configured to sample the chip select signal from one or more of a first sampling point between the receiver and the logic circuit and a second sampling point between the logic circuit and the output driver.

Abstract: The memory device includes a plurality of memory blocks, each including a plurality of memory cells arranged in a plurality of word lines. Control circuitry is in communication with the plurality of memory blocks. In operation, the control circuitry receives a data write instruction and programs the memory cells of the memory blocks to a one bit per memory cell (SLC) format. In response to the data programmed to the memory cells of the memory blocks in the SLC format reaching an SLC limit prior to completion of the data write instruction, without erasing the memory cells programmed to the SLC format, the control circuitry programs the memory cells of at least some of the plurality of memory blocks from the SLC format to a two bits per memory cell (MLC) format.

Abstract: Provided are an information suggestion system, an information suggestion method, a program, and a recording medium capable of suggesting information of interest to many users to a product provider related to the information from an image group of a plurality of users. In the information suggestion system, the information suggestion method, the program, and the recording medium, an image group acquisition unit acquires an image group of a plurality of users, and an image analysis unit detects an imaging location of each image and an object appearing in each image. An imaging number count unit counts an imaging number of same-type images which are captured at the same imaging location and in which the same object appears, and an imaging frequency calculation unit calculates an imaging frequency of the same-type images.

Abstract: A multi-mode tracking method according to the present disclosure includes receiving, a sensor signal, obtaining a sensor-based location of a sports participant based on the sensor signal, obtaining a first credibility information related to a credibility of the sensor-based location, receiving a sports image captured at a camera disposed peripheral to a playfield, the sports image including the sports participant in the playfield, obtaining an image-based location of the sports participant, obtaining an second credibility information related to a credibility of the image-based location, wherein the credibility of the image-based location is related to an occlusion related to the sports participant, calculating an weight value based on the first credibility information and the second credibility information, calculating a location of the sports participant based on the weight value.

Abstract: The sense amplifier circuit includes a differential amplifier, a first switch, and a second switch. The differential amplifier includes a first input node, a second input node, a first output node, and a second output node. The differential amplifier amplifies a voltage difference of the first output node and the second output node according to a first input voltage of the first input node and a second input voltage of the second input node. A control node of the first (second) switch is coupled to a control line, the first (second) switch is coupled to the first (second) input node, and the first (second) switch is coupled to the first (second) output node. The first (second) switch pre-charges the first (second) input node by a first (second) output voltage of the first (second) output node while the control line is received a select signal.

Abstract: A memory device includes: a first memory cell mat that includes first multi-layer level sub word lines positioned over a substrate; a second memory cell mat that is laterally spaced apart from the first memory cell mat and includes second multi-layer level sub word lines; a first sub word line driver circuit that is positioned underneath the first memory cell mat; and a second sub word line driver circuit that is positioned underneath the second memory cell mat, wherein the first sub word line driver circuit is positioned underneath ends of the first multi-layer level sub word lines, and the second sub word line driver circuit is positioned underneath ends of the second multi-layer level sub word lines.

Abstract: An information processing device, including a resistive analog neuromorphic device element having a pair of electrodes and an oxide layer provided between the pair of electrodes, and a parallel circuit having a low resistance component and a capacitance component. The parallel circuit and the resistive analog neuromorphic device element are connected in series.

Abstract: Techniques for denoising a magnetic resonance (MR) image are provided, including: obtaining a noisy MR image; denoising the noisy MR image of the subject using a denoising neural network model, and outputting a denoised MR image. The denoising neural network model is trained by: generating first training data for training a first neural network model to denoise MR images by generating a first plurality of noisy MR images using clean MR data associated with a source domain and first MR noise data associated with the target domain; training the first neural network model using the first training data; generating training data for training the denoising neural network model by applying the first neural network model to a second plurality of noisy MR images and generating a plurality of denoised MR images; and training the denoising neural network model using the training data for training the denoising neural network model.

Abstract: A memory controller may include: a request checker identifying memory devices corresponding to requests received from a host among the plurality of memory devices and generating the identified device information on memory devices to perform operations corresponding to the requests; a dummy manager outputting a request for controlling a dummy pulse to be applied to channels of selected memory devices according to the device information among the plurality of channels; and a dummy pulse generator sequentially applying the dummy pulse to the channels coupled to the selected memory devices, based on the request for controlling the dummy pulse. A memory controller may include an idle time monitor outputting an idle time interval of the memory device and a clock signal generator generating a clock signal based on the idle time interval and outputting the clock signal to the memory device through the channel to perform a current operation.