Abstract: In an embodiment, a memory circuit includes: a memory, N latch circuits coupled in parallel, a data multiplexer, a logic circuit, and a data path data path. The memory array is configured to provide read data to a first data bus, and each latch circuit is configured to store read data from the first data bus. The data multiplexer has N data inputs respectively coupled to data outputs of the N latch circuits and is configured to select a data input of the N data inputs of the data multiplexer to connect to the data output of the data multiplexer based on a selection input of the data multiplexer. The data path is configured to cause a propagation of data from a data output of the data multiplexer to a data input of the logic circuit.

Abstract: Multi-port semiconductor memory cells including a common floating body region configured to be charged to a level indicative of a memory state of the memory cell. The multi-port semiconductor memory cells include a plurality of gates and conductive regions interfacing with said floating body region. Arrays of memory cells and method of operating said memory arrays are disclosed for making a memory device.

Abstract: The present technology is directed to identifying and labeling a vehicle appendage. More specifically, the present technology is generally related to receiving one or more lidar points associated with a vehicle having an appendage and outputting a label to classify the vehicle and the appendage. In some examples, a first portion of the one or more lidar points associated with the vehicle having the appendage represents the vehicle and a second portion of the one or more lidar points associated with the vehicle having the appendage represents the appendage The present disclosure can further train a perception model to output the label to classify the vehicle and the appendage.

Abstract: The present disclosure relates to systems, methods, and non-transitory computer readable media for accurately and flexibly generating harmonized digital images utilizing an object-to-object harmonization neural network. For example, the disclosed systems implement, and learn parameters for, an object-to-object harmonization neural network to combine a style code from a reference object with features extracted from a target object. Indeed, the disclosed systems extract a style code from a reference object utilizing a style encoder neural network. In addition, the disclosed systems generate a harmonized target object by applying the style code of the reference object to a target object utilizing an object-to-object harmonization neural network.

Abstract: The present disclosure is drawn to, among other things, an antifuse circuit. The antifuse circuit includes a plurality of antifuse bitcells and a reference resistor. Each antifuse bitcell includes two or more memory bits and a reference resistor. The two or more memory bits are configured to be in a programmed state and at least one unprogrammed state.

Abstract: Systems and methods are disclosed for fused processing of a continuous mathematical operator. Fused processing of continuous mathematical operations, such as pointwise non-linear functions without storing intermediate results to memory improves performance when the memory bus bandwidth is limited. In an embodiment, a continuous mathematical operation including at least two of convolution, upsampling, pointwise non-linear function, and downsampling is executed to process input data and generate alias-free output data. In an embodiment, the input data is spatially tiled for processing in parallel such that the intermediate results generated during processing of the input data for each tile may be stored in a shared memory within the processor. Storing the intermediate data in the shared memory improves performance compared with storing the intermediate data to the external memory and loading the intermediate data from the external memory.

Abstract: Techniques are disclosed for training and applying a denoising model. The denoising model includes multiple specialized denoisers and a generalizer, each of which is a machine learning model. The specialized denoisers are trained to denoise images associated with specific ranges of noise parameters. The generalizer is trained to generate per-pixel denoising kernels for denoising images associated with arbitrary noise parameters using outputs of the specialized denoisers. Subsequent to training, a noisy image, such as a live-action image or a rendered image, can be denoised by inputting the noisy image into the specialized denoisers to obtain intermediate denoised images that are then input, along with the noisy image, into the generalizer to obtain per-pixel denoising kernels, which can be normalized and applied to denoise the noisy image.

Abstract: A gait analysis apparatus 10 includes, a data acquisition unit 11 that acquires a three-dimensional point cloud data of a human to be analyzed, a center of gravity location calculation unit 12 that calculates coordinates of a center of gravity location on the three-dimensional point cloud data of the human to be analyzed by using coordinates of each point constituting the acquired three-dimensional point cloud data, and a gait index calculation unit 13 that calculates a gait index of the human to be analyzed by using the calculated center of gravity location.

Abstract: A semiconductor memory device includes a memory string, a voltage supply circuit, a plurality of control signal lines, a row decoder, and a control circuit. The voltage supply circuit is configured to generate a plurality of operation voltages to operate the semiconductor memory device. The operation voltages include a negative voltage. The plurality of control signal lines is connected between the voltage supply circuit and the memory string. The row decoder includes a plurality of transistors provided in the plurality of control signal lines, respectively. The control circuit is configured to control the transistors of the row decoder, and cause the negative voltage to be supplied to the row decoder during a certain period of time in which a voltage of one of the control signal lines drops to a negative level.

Abstract: A memory device may include at least one multinary memory cell. Each multinary memory cell includes a parallel connection of N sub-bit units. N is an integer greater than 1. Each of the N sub-bit units includes a series connection of a respective transistor and a respective capacitor. A first sub-bit unit includes a first capacitor having a capacitance of C, and each i-th sub-unit includes an i-th capacitor having a capacitance of about 2i-1×C. A multinary bit having 2N values may be stored. A device network including multiple multinary logic units is also provided. Each of multiple multinary logic unit includes a parallel connection of N sub-bit units. Each sub-bit unit includes a series connection of a respective transistor and a respective capacitor having capacitance ratios of powers of 2.

Abstract: A semiconductor device with a small circuit area and low power consumption is provided. The semiconductor device includes first to fourth cells, a current mirror circuit, and first to fourth wirings, and the first to fourth cells each include a first transistor, a second transistor, and a capacitor. In each of the first to fourth cells, a first terminal of the first transistor is electrically connected to a first terminal of the capacitor and a gate of the second transistor. The first wiring is electrically connected to first terminals of the second transistors in the first cell and the second cell, the second wiring is electrically connected to first terminals of the second transistors in the third cell and the fourth cell, the third wiring is electrically connected to second terminals of the capacitors in the first cell and the third cell, and the fourth wiring is electrically connected to second terminals of the capacitors in the second cell and the fourth cell.

Abstract: A system for reconstructing a magnetic particle image based on a pre-trained model aims to address the influence by point spread function and reduce the computational and time costs, which results in low reconstruction accuracy, or high acquisition time and computational costs for high-precision images. The system is implemented by: generating a simulation system matrix; pre-training a pre-constructed neural network model, and fine-tuning a pre-trained neural network model by performing a downstream task; and inputting real data corresponding to the downstream task into the pre-trained neural network model after fine-tuning, thereby playing an auxiliary role to acquire a high-quality reconstructed MPI image. The system fits the relationship between different harmonics, which helps enhance frequency-domain information.

Abstract: Systems and methods for image processing are described. The systems and methods include receiving a low-resolution image; generating a feature map based on the low-resolution image using an encoder of a student network, wherein the encoder of the student network is trained based on comparing a predicted feature map from the encoder of the student network and a fused feature map from a teacher network, and wherein the fused feature map represents a combination of first feature map from a high-resolution encoder of the teacher network and a second feature map from a low-resolution encoder of the teacher network; and decoding the feature map to obtain prediction information for the low-resolution image.

Abstract: A dual watermarking method for trajectory data based on robust watermarking and fragile watermarking uses an encryption algorithm to construct robust watermark information, and then a farthest pair of feature points in a minimum convex hull of is set as constant points. Further quantization index modulation technology is used to embed robust watermark information into angles constructed from feature points and constant points. Finally, the angles and distance ratios constructed by trajectory points and constant points are used to group trajectory points. Within each group, spatiotemporal attributes of the trajectory points are taken as fragile watermark bits to be embedded in the distance ratios constructed by the trajectory points. A process of watermark detection is consistent with the embedding of watermark information. Watermarks embedded in the trajectory data based on the dual watermarking method have high robustness against translation, rotation, and scaling attacks.

Abstract: A raycaster performs a raycasting algorithm, where the raycasting algorithm takes, as an input, a sparse hierarchical volumetric data structure. Performing the raycasting algorithm includes casting a plurality of rays from a reference point into the 3D volume, and, for each of the plurality of rays, traversing the ray to determine whether voxels in the set of voxels are intersected by the ray and are occupied, where the ray is to be traversed according to an approximate traversal algorithm.

Abstract: Systems and methods for resolving data (DQ) line swapping configuration in Double Data Rate (DDR) memories are described. In an illustrative, non-limiting embodiment, a system may include a memory controller and a memory coupled to the memory controller, the memory having program instructions stored thereon that, upon execution, cause the system to: apply a first technique to resolve DQ line swapping between a memory interface and a memory module with respect to a first subset of a plurality of DQ lines; apply a second technique different than the first technique to resolve DQ line swapping with respect to a second subset of the plurality of DQ lines; and apply a third technique different than the first and the second techniques to resolve DQ line swapping with respect to a third subset of the plurality of DQ lines.

Abstract: A device for performing a matrix-vector multiplication of a matrix with a vector. The device comprising a memory crossbar array comprising a plurality of row lines, a plurality of column lines and a plurality of junctions arranged between the plurality of row lines and the plurality of column lines. Each junction comprises a programmable resistive element and an access element for accessing the programmable resistive element. The memory crossbar array further comprises one or more write-assist wires and one or more corresponding arrays of switching elements. The write-assist wires are connectable via the switching elements to the plurality of column lines.

Abstract: A memory is provided that includes bitcell VDD boosting to increase a read margin. In some implementations, the positive boost for the bitcell VDD may be provided by a capacitor that is also used for negative boosting of a write driver.

Abstract: A semiconductor memory device includes: a first wiring; a first semiconductor layer connected to the first wiring, the first semiconductor layer; a first electrode, the first electrode being connected to the first semiconductor layer; a second electrode disposed between the first electrode and the first wiring, the second electrode being opposed to the first semiconductor layer; a third electrode disposed between the second electrode and the first wiring, the third electrode; a second semiconductor layer disposed between the third electrode and the first semiconductor layer, the second semiconductor layer being opposed to the third electrode; and an electric charge accumulating layer electrically connected to the first wiring via the second semiconductor layer, the electric charge accumulating layer being opposed to the first semiconductor layer.

Abstract: The present disclosure relates to systems, non-transitory computer-readable media, and methods for training and utilizing generative machine learning models to generate embeddings from phenomic images (or other microscopy representations). For example, the disclosed systems can train a generative machine learning model (e.g., a masked autoencoder generative model) to generate predicted (or reconstructed) phenomic images from masked version of ground truth training phenomic images. In some cases, the disclosed systems utilize a momentum-tracking optimizer while reducing a loss of the generative machine learning model to enable efficient training on large scale training image batches. Furthermore, the disclosed systems can utilize Fourier transformation losses with multi-stage weighting to improve the accuracy of the generative machine learning model on the phenomic images during training.