Abstract: A circuit module with reliable margin configuration, may include a main circuit, a first auxiliary circuit and a second auxiliary circuit. When the first auxiliary circuit is on, the second auxiliary circuit may be on or off according to whether a control signal is of a first level or a second level. When the first auxiliary circuit and the second auxiliary circuit are both on, the first auxiliary circuit and the second auxiliary circuit may jointly cause an operation parameter of the main circuit to be a first value. When the first auxiliary circuit is on and the second auxiliary circuit is off, the first auxiliary circuit may cause the operation parameter to be a second value. An operation margin of the main circuit may cover a range between the first value and the second value.

Abstract: A memory system includes a non-volatile memory and a memory controller configured to receive a command including an access target in the non-volatile memory and setting information from an external device and configured to control a writing operation or a reading operation to the access target. The memory controller has a condition setting circuit. The condition setting circuit is capable of performing the writing operation or the reading operation under a plurality of different conditions. The memory controller performs the writing operation or the reading operation under one of the plurality of different conditions selected by the condition setting circuit in accordance with the setting information.

Abstract: The present concepts relate to lossless data compression techniques for reducing the size of a data structure. Certain data in the data structure that can be either recovered from another source or rebuilt from other available information may be removed from the data structure. To further reduce data size, the retained data in the data structure may be packed into a smaller-bit encoding data type. Additionally, to reduce the data size even more, the packed data may be zipped using a lossless data compression algorithm. To regain the original data structure, the process may be reversed. The zipped data may be unzipped using a lossless data decompression algorithm. The packed data may be unpacked into the original bit-sized data encoding. The removed data may be restored by either recovering it from another source or rebuilding it from other available information.

Abstract: Disclosed in the embodiments of the present disclosure are a video processing method and apparatus, and an electronic device and a storage medium. The method include: determining a blurred video frame in an initial video; removing the blurred video frame from the initial video, so as to obtain an intermediate video, which dose not comprise the blurred video frame; on the basis of a video frame in the intermediate video that has a timestamp adjacent to a target timestamp, determining a video frame to be inserted, wherein the target timestamp is the timestamp of the blurred video frame; and inserting into a position in the intermediate video that corresponds to the target timestamp, the video frame to be inserted, so as to obtain a target video.

Abstract: A surgical simulator for simulating a surgical scenario comprises a display system, a user interface, and a controller. The controller includes one or more processors coupled to memory that stores instructions that when executed cause the system to perform operations. The operations include generating simulated surgical videos, each representative of the surgical scenario. The operations further include associating simulated ground truth data from the simulation with the simulated surgical videos. The ground truth data corresponds to context information of at least one of a simulated surgical instrument, a simulated anatomical region, a simulated surgical task, or a simulated action. The operations further include annotating features of the simulated surgical videos based, at least in part, on the simulated ground truth data for training a machine learning model.

Abstract: A p layer extending in a direction horizontal to a substrate is provided separately from the substrate. An n+ layer is provided on one side of the layer. A gate insulating layer partially covers the layers. A gate conductor layer partially covers the layer. A gate insulating layer partially covering the layer is provided separately from the layer. A gate conductor layer partially covers the layer. An n+ layer is provided at part of the p layer between the layers. The layers are connected to a bit line, a source line, a word line, and a plate line, respectively. Memory operation of a dynamic flash memory cell is performed by manipulating voltage of each line.

Abstract: Provided are an apparatus and method for honeycomb artifacts removal for removing honeycomb artifacts in images received from an optical fiber imaging device through a honeycomb artifact removal model. The honeycomb artifact removal apparatus according to an embodiment includes a control unit configured to create a training dataset, build the honeycomb artifact removal model with the created training data, remove a honeycomb artifact in an input image through the built honeycomb artifact removal model and output a corrected image, wherein the control unit is configured to perform preprocessing of a raw image, acquire a honeycomb artifact image through the optical fiber imaging device, and synthesize the preprocessed raw image with the honeycomb artifact image to generate a honeycomb artifact synthesized image, and the training dataset is created by mapping the honeycomb artifact synthesized image as input data and the preprocessed raw image as output data.

Abstract: Apparatuses, systems, and techniques to generate blue noise masks for real-time image rendering and enhancement. In at least one embodiment, a noise mask is generated and applied to one or more images to generate one or more enhanced images for image processing (e.g., real-time image rendering). In at least one embodiment, the noise mask is able to handle the temporal domain (e.g., add time to the spatial domain) to improve image quality when rendering images over multiple frames.

Abstract: Disclosed in the present disclosure are an image-text mutual retrieval model training method and apparatus, an image-text mutual retrieval method, and a device, applied to the technical field of retrieval. The image-text mutual retrieval model training method includes: acquiring training data pairs; inputting the training data pair in an initial model, and extracting text coding features of text training data and image coding features of image training data by using a text coding module and an image coding module in the initial model, respectively; calculating a training loss based on the text coding features and the image coding features, and performing parameter adjustment on the initial model based on the training loss; and in response to the training loss meeting a convergence condition, determining the initial model after the parameter adjustment as an image-text mutual retrieval model.

Abstract: On a substrate Sub, a semiconductor base material (Si pillar) that stands on the substrate in a vertical direction or that extends along the substrate in a horizontal direction a first impurity layer and a second impurity layer that are disposed on respective ends of the semiconductor base material, a first gate conductor layer, and a second gate conductor layer that surround the semiconductor base material between the first impurity layer and the second impurity layer, and a channel semiconductor layer are disposed. Voltages are applied to perform a memory write operation of discharging a group of electrons from the channel semiconductor layer and retaining some of a group of positive holes in the channel semiconductor layer generated inside the channel semiconductor layer by a gate-induced drain leakage current, and a memory erase operation of discharging the group of positive holes retained in the channel semiconductor layer.

Abstract: The present disclosure relates to a semiconductor device enabling to suppress waste of energy consumption. There is provided a semiconductor device including: an input unit configured to input a charge; a memory unit configured to collect and accumulate a charge from the input unit; and an output unit configured to detect and output a charge accumulated in the memory unit. The memory unit includes a transfer unit to which a plurality of pairs of a gate unit and an accumulation unit is connected, the gate unit selects the accumulation unit that accumulates a charge, the transfer unit transfers a charge from the input unit to the accumulation unit selected by the gate unit, the accumulation unit accumulates a charge transferred from the transfer unit, and the transfer unit transfers a charge accumulated in the accumulation unit selected by the gate unit, to the output unit. The present disclosure can be applied to, for example, an analog memory device.

Abstract: A method of detecting a defect in a stacked structure of a display panel includes collecting a first image of the defect and a plurality of layers in the stacked structure from a database, learning a defect information of the defect and a layer information of the layers using a deep learning model based on the first image and detecting a location of the defect among the layers by the defect information and the layer information.

Abstract: A dynamic random access memory (DRAM) device may include an array of DRAM cells, with each DRAM cell configured to store a high logic voltage and a low logic voltage. The DRAM device may further include a precharge circuit configured to selectively provide a first reference voltage and a second reference voltage to a first line and a second line, respectively, and a sense amplifier comprising a cross-coupled transistor sensing circuit coupled between the first line and second line. The sense amplifier may include at least one transistor including a superlattice channel. The DRAM device may further include a refresh circuit configured to selectively couple a third reference voltage to a corresponding DRAM cell via the first line and based upon a voltage difference between the first line and the second line, with the third reference voltage being greater than the high logic voltage of the DRAM cell.

Abstract: A semiconductor storage device includes word lines extending in first and second directions, and separated from each other in a third direction, sense amplifier circuits that partially overlap the word lines in the third direction, memory strings intersecting the word lines and extending in the third direction, memory-side bit lines extending in the first direction, separated from each other in the second direction, and including first and second adjacent memory-side bit lines, circuit-side bit lines between the word lines and the sense amplifier circuits and partially overlapping the respective memory-side bit lines in the third direction, and contact plugs extending in the third direction and respectively connecting the memory-side bit lines and the circuit-side bit lines. The contact plugs include first and second contract plugs that are electrically connected to the first and second memory-side bit lines, respectively, and are not aligned along the first or second direction.

Abstract: A memory device having long data retention time and high reliability is provided. The memory device includes a driver circuit and a plurality of memory cells, the memory cell includes a transistor and a capacitor, and the transistor includes a metal oxide in a channel formation region. The transistor includes a first gate and a second gate, and in a period during which the memory cell retains data, negative potentials are applied to the first gate and the second gate of the transistor.

Abstract: A complementary storage unit and a method of preparing the same, and a complementary memory. The complementary storage unit includes: a control transistor, a pull-up diode and a pull-down diode. The control transistor is configured to control reading and writing of the storage unit. One end of the pull-up diode is connected to a positive selection line, and the other end thereof is connected to a source end of the control transistor, so as to control a high-level input. One end of the pull-down diode is connected to a negative selection line, and the other end thereof is connected to the source end of the control transistor, so as to control a low-level input. The pull-up diode and the pull-down diode are symmetrically arranged in a first direction.

Abstract: A memory core characteristic screening method includes the following steps. A command signal transmitting step includes configuring a processing module to transmit a command signal to a memory device. A first internal operating step includes configuring the memory device to operate a first operation to one of a word line, a bit line pair and a column line after a first strobe signal delay time according to a first command. A second internal operating step includes configuring the memory device to operate a second operation to another one of the word line, the bit line pair and the column line after a second strobe signal delay time according to a second command. A memory core characteristic screening step includes screening a memory core characteristic by shorting a timing between the first strobe signal delay time and the second strobe signal delay time.

Abstract: The present invention relates to a method of assisting in diagnosis of a target heart disease using a retinal image, the method including: obtaining a target retinal image which is obtained by imaging a retina of a testee; on the basis of the target retinal image, obtaining heart disease diagnosis assistance information of the testee according to the target retinal image, via a heart disease diagnosis assistance neural network model which obtains diagnosis assistance information that is used for diagnosis of the target heart disease according to the retinal image; and outputting the heart disease diagnosis assistance information of the testee.

Abstract: A memory structure of an integrated circuit includes a plurality of memory arrays arranged in parallel along the first direction and extending along the second direction, a sensitivity amplifier array extending along the second direction is arranged between every two memory arrays, and the sensitivity amplifier array includes an odd-numbered sensitivity amplifier array and an even-numbered sensitivity amplifier array, the odd-numbered sensitivity amplifier array is connected to an odd-numbered global signal line, and the even-numbered sensitivity amplifier array is connected to the even-numbered global signal line; a first sensitivity amplifier array is arranged between the memory arrays at the edge, and the first sensitivity amplifier array is connected to both the odd-numbered global signal line and the even-numbered global signal line. The present disclosure can improve reliability, yield and test success rate of the memory products.

Abstract: The present invention generally relates to the field of replicating or copying keys. More specifically, the present invention relates to creating a copy of a master key based on a captured image of the master key. The present invention identifies a set of target key information based on vehicle and or lock information as well as the image of the master key to provide for the cutting of a duplicate key blade copy to be delivered to a user or to another location. Additional key information may also be captured along with the image of the master key.