Abstract: A memory device includes a memory cell array. The memory cell array includes first-tier word lines extending in a first direction, second-tier word lines disposed below the first-tier word lines and extending in a second direction angularly offset from the first direction, and bit lines extending in a third direction angularly offset from the first and second directions. The bit lines are arranged between a pair of the first-tier word lines and between a pair of the second-tier word lines.

Abstract: Some embodiments include apparatuses and methods of operating such apparatuses. One of such apparatuses includes a data line, a conductive region, and a memory cell including a first transistor and a second transistor. The first transistor includes a first channel region coupled to the data line and the conductive region, a charge storage structure, and a first gate. The second transistor includes a second channel region coupled to the data line and the charge storage structure, and a second gate. The first gate is electrically separated from the second gate and opposite from the second gate in a direction from the first channel region to the second channel region.

Abstract: An estimation step according to an embodiment causes a computer to execute: a calculation step of using a plurality of images obtained by a plurality of imaging devices imaging a three-dimensional space in which a plurality of objects reside, to calculate representative points of pixel regions representing the objects among pixel regions of the images; a position estimation step of estimating positions of the objects in the three-dimensional space, based on the representative points calculated by the calculation step; an extraction step of extracting predetermined feature amounts from image regions representing the objects; and an attitude estimation step of estimating attitudes of the objects in the three-dimensional space, through a preliminarily learned regression model, using the positions estimated by the position estimation step, and the feature amounts extracted by the extraction step.

Abstract: A multi-fuse memory cell is disclosed. The circuit includes: a first fuse element electrically coupled to a first transistor, a gate of the first transistor is electrically coupled to a first selection signal; a second fuse element electrically coupled to a second transistor, a gate of the second transistor is electrically coupled to a second selection signal, both the first transistor and the second transistor are grounded; and a programming transistor electrically coupled to the first fuse element and the second fuse element, wherein a gate of the programming transistor is electrically coupled to a programming signal.

Abstract: An imaging parameter output method is a method of outputting an imaging parameter of an imaging device that captures an image for measuring a displacement representing a movement of an object. The imaging parameter output method includes: obtaining object information identifying the object, and a geometric imaging condition for imaging the object; calculating the imaging parameter including a candidate imaging area for placing the imaging device and the accuracy in measuring the displacement in the candidate imaging area, based on the object information and the geometric imaging condition, without imaging the object using the imaging device; and outputting the imaging parameter.

Abstract: Methods and systems are provided for transmitting data using thin-oxide devices. The methods and system generate a first bias voltage and a second bias voltage based on a power supply voltage of the second voltage domain, the first bias voltage value representing a high-level voltage signal of the first voltage domain, and the second bias voltage representing a low-level voltage signal of the second voltage domain and its value corresponds to a difference between the second voltage domain and the first voltage domain. The methods and systems generate an output of the thin-oxide device interface using first and second thin-oxide devices, the output of the thin-oxide device interface having a range corresponding to the second voltage domain.

Abstract: A photogrammetric ground control point quality evaluation method based on Monte Carlo test relates to the field of photogrammetry technology. Firstly, aerial photographs and ground control points from a survey area are obtained, the ground control points are numbered, the aerial photographs are performed with point-placing and aerial triangulation densification. Secondly, a Monte Carlo test experiment is designed, a certain number of the ground control points are selected as control points with the rest as check points, ensuring each ground control point as the control point a certain number of times, and average errors of the ground control points are calculated. Thirdly, average values of the average errors of the ground control points are calculated, standard deviations of the average errors of the ground control points are calculated. Finally, a quality coefficient Q of each ground control point is calculated and evaluated according to quality evaluation standards.

Abstract: A memory circuit includes a first and a second bit line coupled to a set of memory cells, a local input output circuit including a first and a second data line, a first control circuit configured to generate a first sense amplifier signal and a second sense amplifier signal, a second control circuit configured to generate a first control signal in response to at least a second control signal or a third control signal, a switching circuit configured to transfer a first and second input signal to the corresponding first and second data line during a write operation, and to electrically isolate the first and second data line from the first and second input signal during a read operation, and a first latch configured as a sense amplifier, during the read operation, and configured as a write-in latch, during the write operation.

Abstract: Disclosed are a training data generation method and apparatus for an artificial intelligence visual analysis model. The training data generation method includes: (a) receiving a background image and object-related information; (b) generating a target object image that meets a condition based on the object-related information; (c) applying the background image to a depth estimation model to estimate depths of each pixel location and generate a depth map; (d) determining an insertion location and scale at which the target object image is inserted based on the depth map to generate a local object insertion image and a mask image, respectively; (e) simply synthesizing the local object insertion image and the background image and then generating a synthesis image reflecting a scale feature of the background image through a trained multi-scale visual analysis model; and (f) generating a final training image using the background image, the synthesis image, and the mask image.

Abstract: A semiconductor memory device according to the present invention has a memory cell array, a write-driving/bias-reading circuit, a control circuit and a sense amplifier. The control circuit outputs a VSLC (Verify Sense Load Control) signal generated according to writing data. After the write-driving/bias-reading circuit applied the writing pulse and the complementary writing pulse, the sense amplifier receives the VSLC signal and detects the current difference between two currents respectively flowing through a first data line and a second data line; the first data line and the second data line respectively connecting a true memory cell and a complementary memory cell of the selected pair of memory cell. The control circuit controls to provide the additional current to at least one of the first data line and the second data line so as to make the detected current difference meet the required margin.

Abstract: Dense feature scale detection can be implemented using multiple convolutional neural networks trained on scale data to more accurately and efficiently match pixels between images. An input image can be used to generate multiple scaled images. The multiple scaled images are input into a feature net, which outputs feature data for the multiple scaled images. An attention net is used to generate an attention map from the input image. The attention map assigns emphasis as a soft distribution to different scales based on texture analysis. The feature data and the attention data can be combined through a multiplication process and then summed to generate dense features for comparison.

Abstract: A system for generating a pixel map of a yard or facility in substantially real-time. The pixel map may be generated on-the-fly with virtual slots based on various vehicles and containers entering and exiting the yard or facility. In some cases, the pixel map may be utilized to track assets within the facility even if the physical identifier of the asset is unknown or the asset transitions between field of view of various image devices associated with the system.

Abstract: The embodiments described herein describe technologies for memory systems. One implementation of a memory system includes a motherboard substrate with multiple module sockets, at least one of which is populated with a memory module. A first set of data lines is disposed on the motherboard substrate and coupled to the module sockets. The first set of data lines includes a first subset of point-to-point data lines coupled between a memory controller and a first socket and a second subset of point-to-point data lines coupled between the memory controller and a second socket. A second set of data lines is disposed on the motherboard substrate and coupled between the first socket and the second socket. The first and second sets of data lines can make up a memory channel.

Abstract: A memory device may include a memory block operatively connected to a common source line and a plurality of bit lines, wherein the memory block may include first and second sub-blocks each having a respective position in the memory block relative to the common source line and the plurality of bit lines. The memory device mat be operated by receiving a command and an address from outside the memory device and performing a precharge operation on the memory block in response to the command, using a first precharge path through the memory block or a second precharge path through the memory block based on the respective position of the first or second sub-block that includes a word line that is configured to activate responsive to the address.

Abstract: The present disclosure provides a memory array, a memory cell, and a data read and write method thereof. Two storage nodes are provided in each memory cell of a memory array of a magnetic random access memory (MRAM), such that when one storage node in the memory cell fails, the other storage node in the memory cell can be used to write and read data.

Abstract: The present disclosure relates to an image stitching method for relaying 3D VR images in real time. The present disclosure includes the steps of: receiving, by an image reception unit, a captured first circle image and second circle image from a binocular camera; applying, by an ST map application unit, an ST map to each of the first circle image and the second circle image; and converting, by a sphere map conversion unit, the ST-map-applied first circle image and second circle image into a first sphere image and a second sphere image, respectively, through stitching.

Abstract: Structures for a static random access memory bit cell and methods of forming a structure for a static random access memory bit cell. The structure comprises a static random access memory bit cell including a first node and a second node, a first ferroelectric field-effect transistor including a first terminal connected to the first node, and a second ferroelectric field-effect transistor including a second terminal connected to the second node.

Abstract: A memory device includes a memory die bonded to a logic die via a wafer-on-wafer bond. A controller of the memory device that is coupled to the memory die can activate a row of the memory die. Responsive to activating the row, a sense amplifier stripe of the memory die can latch a first plurality of signals. A transceiver can route a second plurality of signals from the sense amplifier stripe to the logic die.

Abstract: A semiconductor memory, comprising a negative voltage providing unit, which is used for providing a first negative voltage to a word line during a read operation, and comprises: a clamping unit that comprises an input end, a control end and an output end, wherein the input end is coupled to a common ground end of the memory, and the control end is used for receiving a first signal; an energy storage capacitor, a first end of which is coupled to the output end, and a second end that is used for receiving a second signal; and a negative voltage providing end which is coupled to the first end, wherein the clamping unit is used for: pulling the voltage at the output end to the voltage at the input end when the first signal is “0”; and clamping the output end at a clamping voltage when the first signal is “1”.

Abstract: A complementary metal oxide semiconductor (CMOS) circuit of a memory device includes a high-voltage functional circuit and an auxiliary clamping circuit. The high-voltage functional circuit includes at least one MOS transistor. One of a source terminal and a drain terminal of an MOS transistor is coupled to an input high-voltage. The high-voltage functional circuit has an output voltage that, when an enable signal is valid, gradually increases and reaches a maximum value. The auxiliary clamping circuit is arranged between the input high-voltage and the one of the source terminal and the drain terminal of the MOS transistor, and is configured to clamp the voltage input to the one of the source terminal and the drain terminal of the MOS transistor during a rising phase of the output voltage, so that the clamping voltage is smaller than the input high-voltage.