Abstract: The memory device includes a plurality of memory blocks, each including a plurality of memory cells arranged in a plurality of word lines. Control circuitry is in communication with the plurality of memory blocks. In operation, the control circuitry receives a data write instruction and programs the memory cells of the memory blocks to a one bit per memory cell (SLC) format. In response to the data programmed to the memory cells of the memory blocks in the SLC format reaching an SLC limit prior to completion of the data write instruction, without erasing the memory cells programmed to the SLC format, the control circuitry programs the memory cells of at least some of the plurality of memory blocks from the SLC format to a two bits per memory cell (MLC) format.

Abstract: In an embodiment, an apparatus an apparatus including a memory module is described. The memory module can include a plurality of memory ranks and a register clock driver (RCD) coupled to the plurality of memory ranks. The RCD can include a receiver configured to receive a chip select signal for selecting one or more memory ranks. The RCD can further include a logic circuit coupled to the receiver, and an output driver coupled to the logic circuit. The RCD can further include a loopback circuit configured to sample the chip select signal from one or more of a first sampling point between the receiver and the logic circuit and a second sampling point between the logic circuit and the output driver.

Abstract: A multi-mode tracking method according to the present disclosure includes receiving, a sensor signal, obtaining a sensor-based location of a sports participant based on the sensor signal, obtaining a first credibility information related to a credibility of the sensor-based location, receiving a sports image captured at a camera disposed peripheral to a playfield, the sports image including the sports participant in the playfield, obtaining an image-based location of the sports participant, obtaining an second credibility information related to a credibility of the image-based location, wherein the credibility of the image-based location is related to an occlusion related to the sports participant, calculating an weight value based on the first credibility information and the second credibility information, calculating a location of the sports participant based on the weight value.

Abstract: Provided are an information suggestion system, an information suggestion method, a program, and a recording medium capable of suggesting information of interest to many users to a product provider related to the information from an image group of a plurality of users. In the information suggestion system, the information suggestion method, the program, and the recording medium, an image group acquisition unit acquires an image group of a plurality of users, and an image analysis unit detects an imaging location of each image and an object appearing in each image. An imaging number count unit counts an imaging number of same-type images which are captured at the same imaging location and in which the same object appears, and an imaging frequency calculation unit calculates an imaging frequency of the same-type images.

Abstract: The sense amplifier circuit includes a differential amplifier, a first switch, and a second switch. The differential amplifier includes a first input node, a second input node, a first output node, and a second output node. The differential amplifier amplifies a voltage difference of the first output node and the second output node according to a first input voltage of the first input node and a second input voltage of the second input node. A control node of the first (second) switch is coupled to a control line, the first (second) switch is coupled to the first (second) input node, and the first (second) switch is coupled to the first (second) output node. The first (second) switch pre-charges the first (second) input node by a first (second) output voltage of the first (second) output node while the control line is received a select signal.

Abstract: Techniques for denoising a magnetic resonance (MR) image are provided, including: obtaining a noisy MR image; denoising the noisy MR image of the subject using a denoising neural network model, and outputting a denoised MR image. The denoising neural network model is trained by: generating first training data for training a first neural network model to denoise MR images by generating a first plurality of noisy MR images using clean MR data associated with a source domain and first MR noise data associated with the target domain; training the first neural network model using the first training data; generating training data for training the denoising neural network model by applying the first neural network model to a second plurality of noisy MR images and generating a plurality of denoised MR images; and training the denoising neural network model using the training data for training the denoising neural network model.

Abstract: A memory device includes: a first memory cell mat that includes first multi-layer level sub word lines positioned over a substrate; a second memory cell mat that is laterally spaced apart from the first memory cell mat and includes second multi-layer level sub word lines; a first sub word line driver circuit that is positioned underneath the first memory cell mat; and a second sub word line driver circuit that is positioned underneath the second memory cell mat, wherein the first sub word line driver circuit is positioned underneath ends of the first multi-layer level sub word lines, and the second sub word line driver circuit is positioned underneath ends of the second multi-layer level sub word lines.

Abstract: An information processing device, including a resistive analog neuromorphic device element having a pair of electrodes and an oxide layer provided between the pair of electrodes, and a parallel circuit having a low resistance component and a capacitance component. The parallel circuit and the resistive analog neuromorphic device element are connected in series.

Abstract: A non-volatile static random access memory includes: a static random access memory, a reading element and a first embedded non-volatile memory. The static random access memory includes a first inverter, a second inverter and two transistors, an output terminal of the first inverter and the input terminal of the second inverter are electrically connected to each other to serve as a Q node, an input terminal of the first inverter and an output terminal of the second inverter are electrically connected to each other to serve as a QB node, and the two transistors are electrically connected to the Q node and the QB node, respectively. The reading element is electrically connected to the Q node. The first embedded non-volatile memory is electrically connected to the QB node.

Abstract: A memory controller may include: a request checker identifying memory devices corresponding to requests received from a host among the plurality of memory devices and generating the identified device information on memory devices to perform operations corresponding to the requests; a dummy manager outputting a request for controlling a dummy pulse to be applied to channels of selected memory devices according to the device information among the plurality of channels; and a dummy pulse generator sequentially applying the dummy pulse to the channels coupled to the selected memory devices, based on the request for controlling the dummy pulse. A memory controller may include an idle time monitor outputting an idle time interval of the memory device and a clock signal generator generating a clock signal based on the idle time interval and outputting the clock signal to the memory device through the channel to perform a current operation.

Abstract: CMOS harvesting circuits are disclosed for conventional 6T SRAM bitcell arrays enabling substantial improvements to SRAM access time, pipeline performance and to SRAM active and leakage energy consumption—without scaling operating voltages while also improving Read and Write margins using assist schemes at very low area and energy overhead by reusing circuits that harvest charge. Active energy dissipation during an SRAM read access is lowered by use of novel sensing schemes that self-limit signal development on the BL without the energy overheads seen in conventional designs from sense-amp offsets, BL column leakage and uncertain read current. Improvements in access time are enabled by increasing the signal development rate on the BL—by comparing the rising electric potential of harvested charge with a decreasing BL voltage in a bitcell column using a novel and compact inverting amplifier with dynamic reset.

Abstract: A memory device includes a memory cell array. The memory cell array includes first-tier word lines extending in a first direction, second-tier word lines disposed below the first-tier word lines and extending in a second direction angularly offset from the first direction, and bit lines extending in a third direction angularly offset from the first and second directions. The bit lines are arranged between a pair of the first-tier word lines and between a pair of the second-tier word lines.

Abstract: Some embodiments include apparatuses and methods of operating such apparatuses. One of such apparatuses includes a data line, a conductive region, and a memory cell including a first transistor and a second transistor. The first transistor includes a first channel region coupled to the data line and the conductive region, a charge storage structure, and a first gate. The second transistor includes a second channel region coupled to the data line and the charge storage structure, and a second gate. The first gate is electrically separated from the second gate and opposite from the second gate in a direction from the first channel region to the second channel region.

Abstract: A multi-fuse memory cell is disclosed. The circuit includes: a first fuse element electrically coupled to a first transistor, a gate of the first transistor is electrically coupled to a first selection signal; a second fuse element electrically coupled to a second transistor, a gate of the second transistor is electrically coupled to a second selection signal, both the first transistor and the second transistor are grounded; and a programming transistor electrically coupled to the first fuse element and the second fuse element, wherein a gate of the programming transistor is electrically coupled to a programming signal.

Abstract: An estimation step according to an embodiment causes a computer to execute: a calculation step of using a plurality of images obtained by a plurality of imaging devices imaging a three-dimensional space in which a plurality of objects reside, to calculate representative points of pixel regions representing the objects among pixel regions of the images; a position estimation step of estimating positions of the objects in the three-dimensional space, based on the representative points calculated by the calculation step; an extraction step of extracting predetermined feature amounts from image regions representing the objects; and an attitude estimation step of estimating attitudes of the objects in the three-dimensional space, through a preliminarily learned regression model, using the positions estimated by the position estimation step, and the feature amounts extracted by the extraction step.

Abstract: An imaging parameter output method is a method of outputting an imaging parameter of an imaging device that captures an image for measuring a displacement representing a movement of an object. The imaging parameter output method includes: obtaining object information identifying the object, and a geometric imaging condition for imaging the object; calculating the imaging parameter including a candidate imaging area for placing the imaging device and the accuracy in measuring the displacement in the candidate imaging area, based on the object information and the geometric imaging condition, without imaging the object using the imaging device; and outputting the imaging parameter.

Abstract: Methods and systems are provided for transmitting data using thin-oxide devices. The methods and system generate a first bias voltage and a second bias voltage based on a power supply voltage of the second voltage domain, the first bias voltage value representing a high-level voltage signal of the first voltage domain, and the second bias voltage representing a low-level voltage signal of the second voltage domain and its value corresponds to a difference between the second voltage domain and the first voltage domain. The methods and systems generate an output of the thin-oxide device interface using first and second thin-oxide devices, the output of the thin-oxide device interface having a range corresponding to the second voltage domain.

Abstract: A photogrammetric ground control point quality evaluation method based on Monte Carlo test relates to the field of photogrammetry technology. Firstly, aerial photographs and ground control points from a survey area are obtained, the ground control points are numbered, the aerial photographs are performed with point-placing and aerial triangulation densification. Secondly, a Monte Carlo test experiment is designed, a certain number of the ground control points are selected as control points with the rest as check points, ensuring each ground control point as the control point a certain number of times, and average errors of the ground control points are calculated. Thirdly, average values of the average errors of the ground control points are calculated, standard deviations of the average errors of the ground control points are calculated. Finally, a quality coefficient Q of each ground control point is calculated and evaluated according to quality evaluation standards.

Abstract: A memory circuit includes a first and a second bit line coupled to a set of memory cells, a local input output circuit including a first and a second data line, a first control circuit configured to generate a first sense amplifier signal and a second sense amplifier signal, a second control circuit configured to generate a first control signal in response to at least a second control signal or a third control signal, a switching circuit configured to transfer a first and second input signal to the corresponding first and second data line during a write operation, and to electrically isolate the first and second data line from the first and second input signal during a read operation, and a first latch configured as a sense amplifier, during the read operation, and configured as a write-in latch, during the write operation.

Abstract: Disclosed are a training data generation method and apparatus for an artificial intelligence visual analysis model. The training data generation method includes: (a) receiving a background image and object-related information; (b) generating a target object image that meets a condition based on the object-related information; (c) applying the background image to a depth estimation model to estimate depths of each pixel location and generate a depth map; (d) determining an insertion location and scale at which the target object image is inserted based on the depth map to generate a local object insertion image and a mask image, respectively; (e) simply synthesizing the local object insertion image and the background image and then generating a synthesis image reflecting a scale feature of the background image through a trained multi-scale visual analysis model; and (f) generating a final training image using the background image, the synthesis image, and the mask image.