Patents Examined by Viet Q. Nguyen
  • Patent number: 11031071
    Abstract: A nonvolatile memory device includes a memory cell region including first metal pads and a memory cell array, and a peripheral circuit region including second metal pads, row decoder circuitry that is connected to the rows of the memory cells through word lines and controls voltages of the word lines, and page buffer circuitry that is connected to the columns of the memory cells through bit lines. The page buffer circuitry is configured to obtain first values by performing a first sensing operation on first bit lines of the bit lines through the first transistors and obtain second values by performing a second sensing operation on the second bit lines of the bit lines through the second transistors, wherein the first values or the second values are inverted. The peripheral circuit region is vertically connected to the memory cell region by the metal pads directly.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: June 8, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Hyun Jun Yoon
  • Patent number: 11030458
    Abstract: The disclosure herein describes training a machine learning model to recognize a real-world object based on generated virtual scene variations associated with a model of the real-world object. A digitized three-dimensional (3D) model representing the real-world object is obtained and a virtual scene is built around the 3D model. A plurality of virtual scene variations is generated by varying one or more characteristics. Each virtual scene variation is generated to include a label identifying the 3D model in the virtual scene variation. A machine learning model may be trained based on the plurality of virtual scene variations. The use of generated digital assets to train the machine learning model greatly decreases the time and cost requirements of creating training assets and provides training quality benefits based on the quantity and quality of variations that may be generated, as well as the completeness of information included in each generated digital asset.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: June 8, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Muhammad Zeeshan Zia, Emanuel Shalev, Jonathan C. Hanzelka, Harpreet S. Sawhney, Pedro U. Escos, Michael J. Ebstyne
  • Patent number: 11031070
    Abstract: A method for equalizing command/address signals in a memory device includes receiving a status of a termination pin for a memory device and automatically performing equalization on signals received on a command/address bus channel of the memory device based on the status. An apparatus for equalizing command/address signals in a memory device includes an input buffer circuit configured to receive the signals from a command/address bus channel. The apparatus also includes a filter circuit configured to automatically perform equalization on the signals based on a status of a termination pin.
    Type: Grant
    Filed: January 27, 2020
    Date of Patent: June 8, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Todd M. Buerkle, Eric J. Stave
  • Patent number: 11023149
    Abstract: Contraction of a doubly mapped redundant array of independent nodes, e.g., a doubly mapped cluster, is disclosed. Different mappings of data for a doubly mapped cluster corresponding to different uses of computing resources. Where a computing resource parameter indicates the computing resource is underutilized, an alternative mapping of the doubly mapped cluster can be undertaken. The alternative mapping can better utilize the computing resources. The contraction of the doubly mapped cluster can maintain access to stored data. The contraction can preserve data protection set integrity. The contraction can result in the doubly mapped cluster comprising fewer mapped nodes after the contraction but can avoid wholesale moving of corresponding data stored in a real cluster. As such, contraction of a doubly mapped cluster can be distinct from scaling-in of a doubly mapped cluster.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: June 1, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Yohannes Altaye, Mikhail Danilov
  • Patent number: 11024376
    Abstract: A memory apparatus includes a memory cell disposed at an intersection of a first wiring line and a second wiring line, and including a variable resistor and a selector, the variable resistor having a resistance state that changes to a first resistance state and a second resistance state, and a drive circuit that writes data to the memory cell by changing the variable resistor from the first resistance state to the second resistance state, and erases the data stored in the memory cell by changing the variable resistor from the second resistance state to the first resistance state. When erasing the data, the drive circuit changing in a stepwise manner a voltage applied to the memory cell, and changing in a stepwise manner a current limit value that limits a magnitude of a current flowing through the memory cell.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: June 1, 2021
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Yotaro Mori, Makoto Kitagawa, Jun Okuno, Haruhiko Terada
  • Patent number: 11017841
    Abstract: A nonvolatile memory device includes a memory cell array that includes memory cells arranged in rows and columns, row decoder circuitry that is connected to the rows of the memory cells through word lines and controls voltages of the word lines, and page buffer circuitry that is connected to the columns of the memory cells through bit lines and includes first transistors configured to sense voltages of the bit lines and second transistors configured to invert and sense the voltages of the bit lines. The page buffer circuitry is configured to obtain first values by performing a first sensing operation on first bit lines of the bit lines through the first transistors and obtain second values by performing a second sensing operation on the second bit lines of the bit lines through the second transistors, wherein the first values or the second values are inverted.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: May 25, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Hyun Jun Yoon
  • Patent number: 11017852
    Abstract: A method of forming a memory device includes: forming a polish stop layer over a metallization layer in an inter-metal dielectric layer; performing an etching process to form an opening in the polish stop layer, in which a sidewall of the opening extends at an acute angle relative to a top surface of the polish stop layer; forming an electrode material in the opening and over the polish stop layer; planarizing the electrode material until a top surface of the polish stop layer is exposed so as to form a bottom electrode surrounded by the polish stop layer; and forming a stack of a resistance switching layer and a top electrode over the bottom electrode.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: May 25, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Chi Tu, Chu-Jie Huang, Sheng-Hung Shih, Nai-Chao Su, Wen-Ting Chu
  • Patent number: 11017868
    Abstract: Methods of operating memory might include storing information indicative of a data value of a digit of data stored in a particular memory cell of the memory prior to programming a subsequent digit of data to the particular memory cell, programming the subsequent digit of data to the particular memory cell, monitoring a voltage level of a supply voltage to the memory while programming the subsequent digit of data, and, if the voltage level of the supply voltage falls below a threshold while programming the subsequent digit of data and the information indicative of the data value of the digit of data has a particular logic level, causing a change in threshold voltage of one memory cell of a pair of gate-connected non-volatile memory cells, and inhibiting the other memory cell of the pair of gate-connected non-volatile memory cells from a change in threshold voltage.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: May 25, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Rainer Bonitz
  • Patent number: 11017509
    Abstract: A method and an apparatus for generating a High Dynamic Range, HDR, image are proposed. The method comprises obtaining a set of two or more input images, the two or more input images including a reference image and one or more non-reference images; for each of the one or more non-reference images, performing an image analysis which comprises, for each region of a plurality of regions of the non-reference image, assessing whether the region of the non-reference image and a corresponding region of the reference image show the same image content and declaring the region of the non-reference image as valid or as invalid based on the assessment; and generating the HDR image by fusing the reference image and the one or more non-reference images, wherein the fusing comprises, for each of the one or more non-reference images, disregarding the invalid regions of the respective non-reference image.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: May 25, 2021
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Fahd Bouzaraa, Onay Urfalioglu, Ibrahim Halfaoui
  • Patent number: 11017528
    Abstract: A method for automatically processing at least one image slice of a given part of at least one lung of a patient suffering from a pathology that causes a bronchial infection by diffuse dilatation of the bronchial tubes of the lungs.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: May 25, 2021
    Inventors: Guillaume Chassagnon, Marie-Pierre Revel, Stéphane Chemouny, Amandine René
  • Patent number: 11011224
    Abstract: A memory device includes a metal structure, a first dielectric layer, a bottom electrode, a second dielectric layer, a resistance switching layer, and a top electrode. The first dielectric layer surrounds the metal structure. The bottom electrode is in contact with a top surface of the metal structure. The second dielectric layer surrounds the bottom electrode, in which a top surface of the bottom electrode is higher than a top surface of the second dielectric layer. The resistance switching layer is over the bottom electrode. The top electrode is over the resistance switching layer.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: May 18, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Chi Tu, Chu-Jie Huang, Sheng-Hung Shih, Nai-Chao Su, Wen-Ting Chu
  • Patent number: 11011219
    Abstract: The present disclosure provides a method for refreshing a memory array. The method includes the following steps: generating a plurality of target row records respectively for a plurality of banks; generating a plurality of row address records based on the plurality of target row records; and performing a row-hammer-refreshing process based on the plurality of row address records.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: May 18, 2021
    Assignee: Nanya Technology Corporation
    Inventors: Nung Yen, Yu-Hsiang Liu
  • Patent number: 11003962
    Abstract: In an approach for classifying an image containing a continuous characteristic using an image classifier, an image tagged with a single value is received, wherein the single value is from a set of ordered value. A processor sets at least two thresholds based on the set of ordered values. A processor derives at least two labels according to the single value tagged in the image and the at least two thresholds. A processor runs image through an image classifier. A processor receives at least two predictions from the image classifier based on the at least two labels. A processor adjusts the image classifier based on differences between the at least two predictions and the at least two labels.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: May 11, 2021
    Assignee: International Business Machines Corporation
    Inventor: Vadim Ratner
  • Patent number: 11003915
    Abstract: This disclosure relates to a method and system for summarizing multimedia content. The method may include receiving multimedia content. The method may further include identifying one or more primary objects, wherein identifying the primary objects comprises identifying one or more actions associated with the primary objects and one or more interactions between the primary objects and one or more secondary objects. The primary objects are associated with one or more parameters. The method may further include determining at least one primary object of interest from the primary objects by selectively prioritizing the parameters. The method may further include summarizing the multimedia content based on the primary object of interest, actions associated with the primary object of interest, interactions between the primary object of interest and the secondary objects, and interactions between the secondary objects and one or more tertiary objects.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: May 11, 2021
    Assignee: Wipro Limited
    Inventor: Manjunath Ramachandra Iyer
  • Patent number: 11005032
    Abstract: Some embodiments relate to a method for manufacturing a magnetoresistive random-access memory (MRAM) cell. The method includes forming a spacer layer surrounding at least a magnetic tunnel junction (MTJ) layer and a top electrode of the MRAM cell; etching the spacer layer to expose a top surface of the top electrode and a top surface of a spacer formed by the spacer layer; forming an upper etch stop layer over the top electrode top surface and the spacer top surface; and forming an upper metal layer in contact with the top electrode top surface of the MRAM cell. A width of the upper etch stop layer is greater than a width of a bottom surface of the upper metal layer.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: May 11, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Harry-Hak-Lay Chuang, Hung Cho Wang, Jiunyu Tsai, Sheng-Huang Huang
  • Patent number: 10997746
    Abstract: Feature descriptor matching described herein may include receiving a first input image and a second input image. A feature detector may detect features from the first and second input images. A descriptor extractor may learn local feature descriptors from the features of the first and second input images based on a feature descriptor matching model trained using a ground truth data set. The descriptor extractor may determine a listwise mean average precision (mAP) rank of a pool of candidate image patches from the second input image with respect to a queried image patch from the first input image based on the feature descriptor matching model, the first set of local feature descriptors, and the second set of local feature descriptors. The descriptor matcher may generate a geometric transformation between the first input image and the second input image based on the listwise mAP and a convolutional neural network.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: May 4, 2021
    Assignee: Honda Motor Co., Ltd.
    Inventors: Kun He, Yan Lu
  • Patent number: 10998893
    Abstract: Methods and apparatus for generating a delayed output signal from an input signal applied to an RC delay circuit of a semiconductor device during an active mode. The RC delay circuit is configured to pull up a voltage level on a node responsive to a reset signal during a stand-by mode.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: May 4, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Hiroshi Akamatsu, Zhi Qi Huang
  • Patent number: 10998026
    Abstract: Methods, systems, and devices for ferroelectric memory plate power reduction are described. A plate line may be coupled with a voltage source, a capacitor, and one or more sections of a bank of ferroelectric memory cells. During a write operation, the capacitor may be discharged onto the plate line and the resulting voltage may be adjusted (e.g., increased) by the voltage source before writing one or more memory cells. During a write-back operation, a capacitor associated with one or more memory cells may be discharged onto the plate line and stored at the capacitor. The charge may be re-applied to the plate line and adjusted (e.g., increased) by the voltage source during the write-back.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: May 4, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Adam S. El-Mansouri, David L. Pinney
  • Patent number: 10997703
    Abstract: A device, system, and method to enable the automatic search of personal profiles in the context of on-line dating that includes the ability to select personal profile images which a likelihood of being perceived as attractive to the person conducting the search. Additionally, by way of further non-limiting example, the device, system, and method is useful in applications such as automatically searching hundreds of actor or model headshots and selecting the ones the director/photographer will approve of for a particular photoshoot, film, or commercial.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: May 4, 2021
    Inventor: Igor Khalatian
  • Patent number: 10998015
    Abstract: A semiconductor storage device includes a memory array at which writing and reading of plural data are carried out, one pair of write registers that temporarily store write data that is to be written into the memory array, and one pair of read registers that temporarily store read data that is read-out from the memory array.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: May 4, 2021
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventors: Toshio Inada, Katsuaki Matsui