Abstract: A memory is provided which comprises a capacitor including non-linear polar material. The capacitor may have a first terminal coupled to a node (e.g., a storage node) and a second terminal coupled to a plate-line. The capacitors can be a planar capacitor or non-planar capacitor (also known as pillar capacitor). The memory includes a transistor coupled to the node and a bit-line, wherein the transistor is controllable by a word-line, wherein the plate-line is parallel to the bit-line. The memory includes a refresh circuitry to refresh charge on the capacitor periodically or at a predetermined time. The refresh circuit can utilize one or more of the endurance mechanisms. When the plate-line is parallel to the bit-line, a specific read and write scheme may be used to reduce the disturb voltage for unselected bit-cells. A different scheme is used when the plate-line is parallel to the word-line.

Abstract: Methods, systems, and devices for driver sharing between banks or portions of banks of memory devices are described. An apparatus may include a first bank and a second bank of memory cells and a word line driver configured to activate word lines. The word line driver may include a master word line driver and an address driver. In some examples, the master word line driver may be configured to generate a first signal to a first portion of the first bank or a second portion of the first bank as part of performing an access operation. In some examples, the master word line driver may be configured to generate a first signal for the first bank or the second bank as part of performing an access operation. The address driver configured to generate a second signal to a portion of the first bank or the second bank.

Abstract: Disclosed are systems and methods to detect and track an object across frames of a video. One of the disclosed methods includes: detecting a first group of one or more objects, using a first neural network, in each frame of the video, wherein each detected head of the first group comprises a leading and a trailing edge; grouping the leading and trailing edges of the one or more objects into groups of leading edges and groups of trailing edges based at least on coordinates of the leading and trailing edges; generating a list of no-edge-detect frames by identifying frames of the video missing a group of leading edges or a group of trailing edges; analyzing the no-edge-detect frames in the list of no-edge-detect frames, using an optical image classification engine, to detect a second group of one or more objects in the no-edge-detect frames; and merging the first and second groups of one or more objects to form a merged list of detected objects in the video.

Abstract: A memory device includes a first data strobe pad; a strobe signal generation circuit suitable for generating a read data strobe signal based on a read timing signal; a monitoring receiver suitable for receiving the read data strobe signal fed back through the first data strobe pad according to a monitoring enable signal; a sampler suitable for generating a sampling clock by sampling the fed back read data strobe signal according to a random clock; a first counter suitable for generating a first counting signal by counting the random clock; a second counter suitable for generating a second counting signal by counting the sampling clock; and a duty detector suitable for generating a duty ratio detection signal based on the first counting signal and the second counting signal.

Abstract: Systems, apparatuses, and methods for organizing bits in a memory device are described. In a number of embodiments, an apparatus can include an array of memory cells, a data interface, a multiplexer coupled between the array of memory cells and the data interface, and a controller coupled to the array of memory cells, the controller configured to cause the apparatus to latch bits associated with a row of memory cells in the array in a number of sense amplifiers in a prefetch operation and send the bits from the sense amplifiers, through a multiplexer, to a data interface, which may include or be referred to as DQs. The bits may be sent to the DQs in a particular order that may correspond to a particular matrix configuration and may thus facilitate or reduce the complexity of arithmetic operations performed on the data.

Abstract: A semiconductor memory device includes a substrate including a logic circuit, a memory cell array disposed over the substrate, a first conductive group including a plurality of bit lines and a first upper source line that are coupled to the memory cell array and spaced apart from each other and a first upper wire that is coupled to the logic circuit, an insulating structure covering the first conductive group.

Abstract: Disclosed is a driving assistance apparatus which can be mounted on a vehicle. The driving assistance apparatus includes an image capturing part, and a processor configured to identify a specific color area in a peripheral image captured by the image capturing part as a first candidate area, identify an area including a specific shape in the first candidate area as a second candidate area, and identify an area of a traffic sign in the second candidate area.

Abstract: Some embodiments include apparatuses and methods of operating such apparatuses. One of such apparatuses includes a data line, a conductive region, and a memory cell including a first transistor and a second transistor. The first transistor includes a first channel region coupled to the data line and the conductive region, a charge storage structure, and a first gate. The second transistor includes a second channel region coupled to the data line and the charge storage structure, and a second gate. The first gate is electrically separated from the second gate and opposite from the second gate in a direction from the first channel region to the second channel region.

Abstract: An estimation device according to an embodiment includes one or more hardware processors configured to function as a query-image-acquisition unit, a query-imaging-condition-acquisition unit, a reference-image-acquisition unit, a reference-imaging-condition-acquisition unit, a feature-amount calculation unit, and a self-position calculation unit. The query-imaging-condition-acquisition unit acquires an imaging condition of a query image. The reference-imaging-condition-acquisition unit acquires an imaging condition of a reference image. The feature-amount calculation unit calculates a query image's feature based on the reference imaging condition, and calculates a reference image's feature based on the query imaging condition.

Abstract: A semiconductor memory device includes: a first wiring; a first semiconductor layer connected to the first wiring, the first semiconductor layer; a first electrode, the first electrode being connected to the first semiconductor layer; a second electrode disposed between the first electrode and the first wiring, the second electrode being opposed to the first semiconductor layer; a third electrode disposed between the second electrode and the first wiring, the third electrode; a second semiconductor layer disposed between the third electrode and the first semiconductor layer, the second semiconductor layer being opposed to the third electrode; and an electric charge accumulating layer electrically connected to the first wiring via the second semiconductor layer, the electric charge accumulating layer being opposed to the first semiconductor layer.

Abstract: Systems and methods for generation and use of document analysis architectures are disclosed. A model builder component may be utilized to receiving user input data for labeling a set of documents as in class or out of class. That user input data may be utilized to train one or more classification models, which may then be utilized to predict classification of other documents. Trained models may be incorporated into a model taxonomy for searching and use by other users for document analysis purposes.

Abstract: A memory is provided which comprises a capacitor including non-linear polar material. The capacitor may have a first terminal coupled to a node (e.g., a storage node) and a second terminal coupled to a plate-line. The capacitors can be a planar capacitor or non-planar capacitor (also known as pillar capacitor). The memory includes a transistor coupled to the node and a bit-line, wherein the transistor is controllable by a word-line, wherein the plate-line is parallel to the bit-line. The memory includes a refresh circuitry to refresh charge on the capacitor periodically or at a predetermined time. The refresh circuit can utilize one or more of the endurance mechanisms. When the plate-line is parallel to the bit-line, a specific read and write scheme may be used to reduce the disturb voltage for unselected bit-cells. A different scheme is used when the plate-line is parallel to the word-line.

Abstract: A nonvolatile memory device includes a first lower interlayer insulation layer and a second lower interlayer insulation layer that are sequentially stacked in a first direction; a lower metal layer disposed in the first lower interlayer insulation layer; and a plurality of lower bonding metals disposed in the first lower interlayer insulation layer and the second lower interlayer insulation layer and spaced apart from each other in a second direction that intersects the first direction. An uppermost surface in the first direction of the lower metal layer is lower than an uppermost surface in the first direction of the plurality of lower bonding metals, and the lower metal layer is placed between the plurality of lower bonding metals.

Abstract: A striped pattern image examination support apparatus includes a feature extraction part, a central line collation part, and a display part. The feature extraction part extracts, from each of a first striped pattern image and a second striped pattern image, at least central lines and feature points, as a feature of each of the first striped pattern image and the second striped pattern image. The central line collation part performs collation of the respective central lines of the first striped pattern image and the second striped pattern image, and computes corresponding central lines between the first striped pattern image and the second striped pattern image. The display part determines a display form of each of the central lines based on the computed corresponding central lines and superimposes and displays the central lines on each of the first striped pattern image and the second striped pattern image, according to the determined display form.

Abstract: A memory device includes transistors and a memory cell array disposed over and electrically coupled to the transistors. The memory cell array includes word lines, bit line columns, and data storage layers interposed between the word lines and the bit line columns. A first portion of the word lines on odd-numbered tiers of the memory cell array is oriented in a first direction, and a second portion of the word lines on even-numbered tiers of the memory cell array is oriented in a second direction that is angularly offset from the first direction. The bit line columns pass through the odd-numbered tiers and the even-numbered tiers, and each of the bit line columns is encircled by one of the data storage layers. A semiconductor die and a manufacturing method of a semiconductor structure are also provided.

Abstract: A memory device includes: a first interconnect; a second interconnect; a first string and a second string whose first ends are coupled to the first interconnect; a third string and a fourth string whose second ends are coupled to the second interconnect; a third interconnect; and driver. The third interconnect is coupled to second ends of the first and second strings and to first ends of the third and fourth strings. Each of the first, second, third, and fourth strings includes a first switch element and a memory cell coupled in series. The memory cell includes a second switch element and a resistance change element coupled in parallel. The third interconnect is coupled to the driver via the first interconnect or the second interconnect.

Abstract: Embodiments of the present disclosure provide a method and apparatus for correcting a distorted document image, where the method for correcting a distorted document image includes: obtaining a distorted document image; and inputting the distorted document image into a correction model, and obtaining a corrected image corresponding to the distorted document image; where the correction model is a model obtained by training with a set of image samples as inputs and a corrected image corresponding to each image sample in the set of image samples as an output, and the image samples are distorted. By inputting the distorted document image to be corrected into the correction model, the corrected image corresponding to the distorted document image can be obtained through the correction model, which realizes document image correction end-to-end, improves accuracy of the document image correction, and extends application scenarios of the document image correction.

Abstract: An exemplary process for identifying a type of a physical environment amongst a plurality of types of physical environments is provided. The process includes obtaining, using the one or more cameras, image data corresponding to a physical environment. The process further includes identifying at least one portion of an entity in the physical environment based on the image data; determining, based on the identified at least one portion of the entity, whether the entity is an entity of a first type; determining a type of the physical environment if the entity is an entity of the first type; and presenting one or more virtual objects and a representation of the entity.

Abstract: Provided herein are orthodontic devices and methods for patients with missing or ectopic teeth. Methods and processes are provided to properly number the teeth of a patient's arch after a dental scan. Methods and processes are also provided to automatically detect missing or ectopic teeth after a dental scan. Methods of designing and manufacturing the aligner are also provided.

Abstract: A semiconductor storage device includes word lines extending in first and second directions, and separated from each other in a third direction, sense amplifier circuits that partially overlap the word lines in the third direction, memory strings intersecting the word lines and extending in the third direction, memory-side bit lines extending in the first direction, separated from each other in the second direction, and including first and second adjacent memory-side bit lines, circuit-side bit lines between the word lines and the sense amplifier circuits and partially overlapping the respective memory-side bit lines in the third direction, and contact plugs extending in the third direction and respectively connecting the memory-side bit lines and the circuit-side bit lines. The contact plugs include first and second contract plugs that are electrically connected to the first and second memory-side bit lines, respectively, and are not aligned along the first or second direction.