Abstract: Vehicular in-cabin facial tracking is performed using machine learning. In-cabin sensor data of a vehicle interior is collected. The in-cabin sensor data includes images of the vehicle interior. A set of seating locations for the vehicle interior is determined. The set is based on the images. The set of seating locations is scanned for performing facial detection for each of the seating locations using a facial detection model. A view of a detected face is manipulated. The manipulation is based on a geometry of the vehicle interior. Cognitive state data of the detected face is analyzed. The cognitive state data analysis is based on additional images of the detected face. The cognitive state data analysis uses the view that was manipulated. The cognitive state data analysis is promoted to a using application. The using application provides vehicle manipulation information to the vehicle. The manipulation information is for an autonomous vehicle.

Abstract: A device may receive a first image. The device may process the first image to identify an object in the first image and a location of the object within the first image. The device may extract a second image from the first image based on the location of the object within the first image. The device may process the second image to determine at least one of a coarse-grained viewpoint estimate or a fine-grained viewpoint estimate associated with the object. The device may determine an object viewpoint associated with the second vehicle based on the at least one of the coarse-grained viewpoint estimate or the fine-grained viewpoint estimate. The device may perform one or more actions based on the object viewpoint.

Abstract: Where an event is determined to have occurred at a location within a vicinity of a plurality of actors, imaging data captured using cameras having the location is processed using one or more machine learning systems or techniques operating on the cameras to determine which of the actors is most likely associated with the event. For each relevant pixel of each image captured by a camera, the camera returns a set of vectors extending to pixels of body parts of actors who are most likely to have been involved with an event occurring at the relevant pixel, along with a measure of confidence in the respective vectors. A server receives the vectors from the cameras, determines which of the images depicted the event in a favorable view, based at least in part on the quality of such images, and selects one of the actors as associated with the event accordingly.

Abstract: Some embodiments include an integrated assembly having first and second source/drain regions laterally offset from one another. Metal silicide is adjacent to lateral surfaces of the source/drain regions. Metal is adjacent to the metal silicide. Container-shaped first and second capacitor electrodes are coupled to the source/drain regions through the metal silicide and the metal. Capacitor dielectric material lines interior surfaces of the container-shaped first and second capacitor electrodes, A shared capacitor electrode extends vertically between the first and second capacitor electrodes, and extends into the lined first and second capacitor electrodes. Some embodiments include methods of forming integrated assemblies.

Abstract: Methods, systems, and devices for thin film transistor deck selection in a memory device are described. A memory device may include memory arrays arranged in a stack of decks formed over a substrate, and deck selection components distributed among the layers to leverage common substrate-based circuitry. For example, each memory array of the stack may include a set of digit lines of a corresponding deck, and deck selection circuitry operable to couple the set of digit lines with a column decoder that is shared among multiple decks. To access memory cells of a selected memory array on one deck, the deck selection circuitry corresponding to the memory array may each be activated, while the deck selection circuitry corresponding to a non-selected memory array on another deck may be deactivated. The deck selection circuitry, such as transistors, may leverage thin-film manufacturing techniques, such as various techniques for forming vertical transistors.

Abstract: The present invention refers to automatics and computing technology, namely to the field of processing images and video data, namely to correction the eyes image of interlocutors in course of video chats, video conferences with the purpose of gaze redirection. A method of correction of the image of eyes wherein the method obtains, at least, one frame with a face of a person, whereupon determines positions of eyes of the person in the image and forms two rectangular areas closely circumscribing the eyes, and finally replaces color components of each pixel in the eye areas for color components of a pixel shifted according to prediction of the predictor of machine learning. Technical effect of the present invention is rising of correction accuracy of the image of eyes with the purpose of gaze redirection, with decrease of resources required for the process of handling a video image.

Abstract: The present disclosure provides a visual model for image analysis of material characterization and analysis method thereof. By collecting and labeling big data of microscopic images, the present disclosure establishes an image data set of material characterization; and uses this data set for high-throughput deep learning, establishes a neural network model and dynamic statistical model based on deep learning, to identify and locate atomic or lattice defects, and automatically mark the lattice spacing, obtain the classification and statistics of the true shape of the microscopic particles of the material, quantitatively analyze the tissue dynamics of the material.

Abstract: An image capture device includes an image sensor and a processor. The image sensor is configured to capture a first plurality of frames, a second plurality of frames, and a third plurality of frames. The processor includes a first denoising layer and a second denoising layer. The first denoising layer includes a first denoiser, a second denoiser, and a third denoiser. The first denoiser is configured to denoise the first plurality of frames and output a first denoised frame. The second denoiser is configured to denoise the second plurality of frames and output a second denoised frame. The third denoiser is configured to denoise the third plurality of frames and output a third denoised frame. The second denoising layer includes a fourth denoiser. The fourth denoiser is configured to output a denoised frame based on the first denoised frame, the second denoised frame, and the third denoised frame.

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to one of a plurality of word lines. The memory cells are disposed in strings and configured to retain a threshold voltage corresponding to one of a plurality of data states. A control means is coupled to the plurality of word lines and the strings and is configured to apply a read voltage to a selected ones of the plurality of word lines during a read operation and ramp down to a discharge voltage at an end of the read operation and apply a ready voltage to the selected ones of the plurality of word lines during a ready period of time following the read operation. The control means is also configured to adjust at least one of the discharge voltage and the ready voltage based on a temperature of the memory apparatus.

Abstract: An apparatus disclosed herein comprises: a plurality of memory cells and a control circuit coupled to the plurality of memory cells. The control circuit is configured to: acquire a first set of read levels on a wordline of a first block of pages of memory cells; acquire a second set of read levels on a first wordline of a second block of pages of a second set of memory cells in response to determining that the fail bit count of the page after a read operation is above the threshold amount; and acquire a third set of read levels on a second wordline of the second block in response to determining that the fail bit count of the page after the second read operation is above the threshold amount.

Abstract: An example system implementing a processing-in-memory pipeline includes: a memory array to store data in a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines; a logic array coupled to the memory array, the logic array to implement configurable logic controlling the plurality of memory cells; and a control block coupled to the memory array and the logic array, the control block to control a computational pipeline to perform computations on the data by activating at least one of: one or more bitlines of the plurality of bitlines or one or more wordlines of the plurality of wordlines.

Abstract: The present disclosure is directed to a circuit layout of a dual port static random-access-memory (SRAM) cell. The memory cell includes active regions in a substrate, with polysilicon gate electrodes on the active regions to define transistors of the memory cell. The eight transistor (8T) memory cell layout includes a reduced aspect ratio and non-polysilicon bit line discharge path routing by positioning an active region for the first port opposite an active region for the second port and consolidating power line nodes at a central portion of the memory cell.

Abstract: A memory die includes an alternating stack of insulating layers and electrically conductive layers through which memory opening fill structures vertically extend. The memory die includes at least three memory array regions interlaced with at least two contact regions, or at least three contact regions interlaced with at least two memory array regions in the same memory plane. A logic die including at least two word line driver regions can be bonded to the memory die. The interlacing of the contact regions and the memory array regions can reduce lateral offset of boundaries of the word line driver regions from boundaries of the contact regions.

Abstract: Embodiments of the present disclosure provide a method and an apparatus for generating a simulation scene. The method includes: acquiring scene parameters of a benchmark scene, where a dimensionality of the scene parameters of the benchmark scene is M; inputting the scene parameters of the benchmark scene into an encoder that is trained, and acquiring encoding parameters according to an output result of the encoder, where a dimensionality of the encoding parameters is N, and N<M; adjusting the encoding parameters to obtain adjusted encoding parameters, and inputting respectively the adjusted encoding parameters into a decoder that is trained; and generating a simulation scene according to the scene parameters of the reconstructed scene that are output by the decoder. According to the method, generating massive simulation scenes similar to the benchmark scene based on the benchmark scene can be achieved, which meets the diversity requirements for the simulation scenes.

Abstract: A phase change memory (PCM) cell comprises a first electrode comprised of a first electrically conductive material, a second electrode comprised of a second electrically conductive material, a first phase change layer positioned between the first electrode and the second electrode and being comprised of a first phase change material, and a second phase change layer positioned between the first electrode and the second electrode and being comprised of a second phase change material. The first phase change material has a first resistivity, the second phase change material has a second resistivity, and wherein the first resistivity is at least two times the second resistivity.

Abstract: A memory device includes: a first memory cell mat that includes first multi-layer level sub word lines positioned over a substrate; a second memory cell mat that is laterally spaced apart from the first memory cell mat and includes second multi-layer level sub word lines; a first sub word line driver circuit that is positioned underneath the first memory cell mat; and a second sub word line driver circuit that is positioned underneath the second memory cell mat, wherein the first sub word line driver circuit is positioned underneath ends of the first multi-layer level sub word lines, and the second sub word line driver circuit is positioned underneath ends of the second multi-layer level sub word lines.

Abstract: Provided are a three-dimensional semiconductor memory device, a method for manufacturing the same, a method for operating the same, and an electronic system including the same. The three-dimensional semiconductor memory device includes a substrate, a stack structure on the substrate, and vertical channel structures, which are provided in channel holes penetrating the stack structure, wherein each of the vertical channel structures includes a data storage pattern, a vertical channel pattern, a conductive pad, and a vertical semiconductor pattern, wherein the vertical channel pattern includes a first portion contacting the upper surface of the substrate and a second portion provided between the data storage pattern and the vertical semiconductor pattern, and wherein the vertical semiconductor pattern is spaced apart from the substrate with the first portion of the vertical channel pattern therebetween.

Abstract: Embodiments provide a read operation circuit, a semiconductor memory, and a read operation method. The read operation circuit includes: a data determination module configured to read read data from a memory bank, and determine whether to invert the read data according to the number of bits of high data in the read data to output global bus data for transmission through a global bus and inversion flag data for transmission through an inversion flag signal line; a data receiving module configured to determine whether to invert the global bus data according to the inversion flag data to output cache data; a parallel-to-serial conversion circuit configured to perform parallel-to-serial conversion on the cache data to generate output data of the DQ port; and a precharge module configured to set an initial state of the global bus to Low.

Abstract: A method includes determining a programmed threshold voltage for a select gate of a memory string and assigning the select gate a programmed reliability rank based upon the programmed threshold voltage. The programmed reliability rank indicates that hot data, warm data, and/or or cold data are programmable to the memory string. The method further includes incrementing a quality characteristic count to a first check voltage value, determining a first checked threshold voltage for the select gate at the first check voltage value, and assigning the select gate a first reliability rank based upon the first checked threshold voltage. The first reliability rank indicates that the warm data or the cold data, or both, are programmable to the memory string.

Abstract: A FeFET configured as a 2-bit storage device that includes a gate stack including a ferroelectric layer over a semiconductor substrate; and the ferroelectric layer includes dipoles; and a first set of dipoles at the first end of the ferroelectric layer has a first polarization; and a second set of dipoles at the second end of the ferroelectric layer has a second polarization, the first and second polarizations of the corresponding first and second sets of dipoles representing storage of 2 bits, wherein a first bit of the 2-bit storage device being configured to be read by application of a read voltage to the source region and a do-not-disturb voltage to the drain region; and a second bit of the 2-bit storage device being configured to be read by application of the do-not-disturb voltage to the source region and the read voltage to the drain region.