Abstract: A method and apparatus for intensifying current leakage between adjacent memory cells includes that: a write operation is performed on a memory array, to form a column strip test pattern, the column strip test pattern being formed by arranging low-level memory cells and high-level memory cells in columns, and N columns of high-level memory cells being present between two adjacent columns of low-level memory cells, N?2; and voltage adjustment is performed on the low-level memory cells and the high-level memory cells, to increase potential differences between the low-level memory cells and the high-level memory cells.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller. The memory controller is configured: to store, in a buffer, a data set read from a cell unit, and an expected data set generated by an error correction on the data set; to count a number of first and second memory cells corresponding to a first and a second combination of data in the data set and the expected data set, respectively, among the memory cells in the cell unit; to calculate a shift amount of a read voltage used in a read operation from the cell unit, based on the number of the first and second memory cells; and to apply the shift amount to a next read operation from the first cell unit.

Abstract: The present disclosure provides methods, systems, and computer program products that use deep learning models to classify candidate mutations detected in sequencing data, particularly suboptimal sequencing data. The methods, systems, and programs provide for increased efficiency, accuracy, and speed in identifying mutations from a wide range of sequencing data.

Abstract: Disclosed is an adaptive application of bias voltages to the access transistors in the cells in dynamic random access memory (DRAM) structures, according to the access pattern of the rows, in other words, whether the rows are accessed and/or how often rows are accessed.

Abstract: Threshold voltage shift values, or TVS values, are calibrated for a non-volatile memory unit including strings of memory cells organized into memory pages, the memory pages being organized into blocks. The calibration involves a read operation to read a given page of the memory pages, based on given one or more TVS values for the given page. In response to a read failure of the read operation, the calibration determines one or more corrected TVS values based on one or more reference TVS values of one or more reference pages of the memory pages. The calibration subsequently performs a read operation to read the given page based on the one or more corrected TVS values. This calibration exploits TVS values of reference pages to determine corrected TVS values of the failing page, instead of finding appropriate TVS values by repeatedly re-reading the failing page.

Abstract: An adaptive control circuit of SRAM (Static Random Access Memory) includes a switch circuit, a forward diode-connected transistor, a backward diode-connected transistor, and a first delay circuit. The switch circuit is supplied by a supply voltage, and is coupled to a first node. The backward diode-connected transistor is coupled in parallel with the forward diode-connected transistor between the first node and a second node. The first delay circuit is coupled between the second node and a ground voltage.

Abstract: Embodiments of systems and methods to determine depth of soil coverage for an underground feature along a right-of-way are disclosed. In an embodiment, the method may include receiving a depth of cover measurement for the right-of-way. The method may include capturing baseline images of the right-of-way within a first selected time of the depth of cover measurement. The method may include rendering a three dimensional elevation model of the right-of-way from the baseline images. The method may include georeferencing the three dimensional elevation model to generate a georeferenced three dimensional elevation model. The method may include adding the depth of cover measurement to the georeferenced three dimensional elevation model. The method may include rendering an updated three dimensional elevation model of the right-of-way from subsequently captured images. The method may include determining a delta depth of coverage based on the georeferenced and the updated three dimensional elevation model.

Abstract: A semiconductor structure includes an electrode, a ferroelectric material adjacent the electrode, the ferroelectric material comprising an oxide of at least one of hafnium and zirconium, the ferroelectric material doped with bismuth, and another electrode adjacent the ferroelectric material on an opposite side thereof from the first electrode. Related semiconductor structures, memory cells, semiconductor devices, electronic systems, and related methods are disclosed.

Abstract: Systems, methods, and computer program products that are configured to identify or otherwise detect the presence of bacteria, classify the identified or detected bacteria, and also predict the growth of the classified bacteria on various touchable surfaces within a vehicle passenger cabin or compartment. Such systems, methods, and computer program products are configured to identify/detect, classify, and predict the presence and/or growth of bacteria, and transmit one or more alerts, warnings, and/or reports to vehicle owners, service providers, and/or occupants based on the identification/detection, classification, and prediction.

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers having channel-material strings therein. Walls are formed above insulating material that is directly above the channel-material strings. Void space is laterally-between immediately-adjacent of the walls and that comprises a longitudinal outline of individual digitlines to be formed. Spaced openings are in the insulating material directly below the void space. Relative to the walls, a conductive metal nitride is selectively deposited in the void space, in the spaced openings, and atop the insulating material laterally-between the walls and the spaced openings to form a lower portion of the individual digitlines laterally-between the immediately-adjacent walls. The conductive metal nitride that is in individual of the spaced openings is directly electrically coupled to individual of the channel-material strings.

Abstract: An information extraction method, an extraction model training method, an apparatus and an electronic device all relate to knowledge graphs. A specific implementation includes acquiring an input text and determining a semantic vector of the input text according to the input text. Such implementation also includes inputting the semantic vector of the input text to a pre-acquired extraction model to obtain a first enhanced text of the input text. The first enhanced text is a text with a text score greater than a preset threshold output by the extraction model. The extraction model performs text extraction based on the semantic vector of the input text. Since the semantic vector has rich context semantics, the enhanced text extracted by the extraction model can be more in line with the context of the input text.

Abstract: The present disclosure relates to systems, non-transitory computer-readable media, and methods for utilizing machine learning and digital embedding processes to generate digital maps of biology and user interfaces for evaluating map efficacy. In particular, in one or more embodiments, the disclosed systems receive perturbation data for a plurality of perturbation experiment units corresponding to a plurality of perturbation classes. Further, the systems generate, utilizing a machine learning model, a plurality of perturbation experiment unit embeddings from the perturbation data. Additionally, the systems align, utilizing an alignment model, the plurality of perturbation experiment unit embeddings to generate aligned perturbation unit embeddings. Moreover, the systems aggregate the aligned perturbation unit embeddings to generate aggregated embeddings. Furthermore, the systems generate perturbation comparisons utilizing the perturbation-level embeddings.

Abstract: A sequence of three-dimension scenes is encoded as a video by an encoder and transmitted to a decoder which retrieves the sequence of 3D scenes. Points of a 3D scene visible from a determined point of view are encoded as a color image in a first track of the stream in order to be decodable independently from other tracks of the stream. The color image is compatible with a three degrees of freedom rendering. Depth information and depth and color of residual points of the scene are encoded in separate tracks of the stream and are decoded only in case the decoder is configured to decode the scene for a volumetric rendering.

Abstract: A memory system and a method of operating the memory system are provided. The memory system includes a plurality of semiconductor memory devices each of which includes a plurality of memory blocks. The memory system also includes a controller configured to control the plurality of semiconductor memory devices to perform a program operation, a read operation, and an operation of removing a hole in a space region on a target memory block of the plurality of memory blocks. The controller controls the plurality of semiconductor memory devices to perform the operation of removing the hole in the space region on the target memory block when an erase count of the target memory block of the plurality of memory blocks is greater than a set value.

Abstract: A storage device includes a storage controller that receives a protecting command before a thermal process is performed in the storage device, and that generates a protecting pattern by programming a protecting voltage in a converged region where threshold voltage distributions of memory cells in the storage device converge after the thermal process is performed on the storage device.

Abstract: A memory device includes: a first interconnect; a second interconnect; a first string and a second string whose first ends are coupled to the first interconnect; a third string and a fourth string whose second ends are coupled to the second interconnect; a third interconnect; and driver. The third interconnect is coupled to second ends of the first and second strings and to first ends of the third and fourth strings. Each of the first, second, third, and fourth strings includes a first switch element and a memory cell coupled in series. The memory cell includes a second switch element and a resistance change element coupled in parallel. The third interconnect is coupled to the driver via the first interconnect or the second interconnect.

Abstract: Methods, systems, and devices for thin film transistor deck selection in a memory device are described. A memory device may include memory arrays arranged in a stack of decks formed over a substrate, and deck selection components distributed among the layers to leverage common substrate-based circuitry. For example, each memory array of the stack may include a set of digit lines of a corresponding deck, and deck selection circuitry operable to couple the set of digit lines with a column decoder that is shared among multiple decks. To access memory cells of a selected memory array on one deck, the deck selection circuitry corresponding to the memory array may each be activated, while the deck selection circuitry corresponding to a non-selected memory array on another deck may be deactivated. The deck selection circuitry, such as transistors, may leverage thin-film manufacturing techniques, such as various techniques for forming vertical transistors.

Abstract: A computer-implemented neural network system for decomposing input video data. A video data input receives a sequence of video image frames. The sequence is encoded, using a 3D spatio-temporal encoder neural network, into a set of latent variables representing a compressed version of the sequence. A 3D spatio-temporal decoder neural network processes the set of latent variables to generate two or more sets of decomposed video data; these may be stored, communicated, and/or made available to a user interface. Input video including undesired features such as reflections, shadows, and occlusions may thus be decomposed into two or more video sequences, one in which the undesired features are suppressed, and another containing the undesired features.

Abstract: The present disclosure generally relates to multi-switch storage cells (MSSCs), three-dimensional MSSC arrays, and three-dimensional MSSC memory. Multi-switch storage cells include a cell select device, multiple resistive change elements, and an intracell wiring electrically connecting the multiple resistive change elements together and to the cell select device. MSSC arrays are designed (architected) and operated to prevent inter-cell (sneak path) currents between multi-switch storage cells, which prevents stored data disturb from adjacent cells and adjacent cell data pattern sensitivity. Additionally, READ and WRITE operations may be performed on one of the multiple resistive change elements in a multi-switch storage cell without disturbing the stored data in the remaining resistive change elements. However, controlled parasitic currents may flow in the remaining resistive change elements within the cell.

Abstract: A memory structure includes a first memory array having bit lines; a second memory array having bit lines; a first sense amplifier connected to a first bit line of the first memory array and a first bit line of the second memory array; and a second sense amplifier connected to a second bit line of the first memory array and a second bit line of the second memory array. The second bit line of the first memory array is adjacent to the first bit line of the first memory array, and the second bit line of the second memory array is adjacent to the first bit line of the second memory array.