Abstract: A semiconductor structure includes: a base substrate; an insulator, located on one side of the base substrate; bit lines, arranged in the insulator, the bit lines being distributed at intervals along first direction and extending along second direction; active bodies, located in the insulator, the active bodies being located on sides of respective bit lines facing away from the base substrate, orthographic projection of each active body on the base substrate at least partially coinciding with the orthographic projection of a respective bit line on the base substrate, and the active bodies being distributed at intervals along second direction; and word lines, located in the insulator and located on sides of respective bit lines facing away from the base substrate, the word lines being distributed at intervals along second direction and extending along first direction, and only one word line being arranged between two adjacent active bodies in second direction.

Abstract: In an embodiment, an apparatus an apparatus including a memory module is described. The memory module can include a plurality of memory ranks and a register clock driver (RCD) coupled to the plurality of memory ranks. The RCD can include a receiver configured to receive a chip select signal for selecting one or more memory ranks. The RCD can further include a logic circuit coupled to the receiver, and an output driver coupled to the logic circuit. The RCD can further include a loopback circuit configured to sample the chip select signal from one or more of a first sampling point between the receiver and the logic circuit and a second sampling point between the logic circuit and the output driver.

Abstract: The present application provides a parameter setting method and apparatus, a system, and a storage medium. The parameter setting method includes: obtaining first setting values of multiple memory parameters and storage locations of the multiple memory parameters in a non-volatile memory; generating a first parameter setting instruction according to the first setting value and the storage location of each memory parameter; and sending the first parameter setting instruction to a test device, so that the test device sets the memory parameter stored at the storage location in the non-volatile memory as the first setting value.

Abstract: A steep-slope field-effect transistor and a fabrication method thereof are disclosed. The steep-slope field-effect transistor according to an embodiment of the inventive concept includes a source, a channel region, and a drain formed on a substrate; a gate insulating film formed on an upper portion of the channel region; a floating gate formed on an upper portion of the gate insulating film; a transition layer formed on an upper portion of the floating gate; and a control gate formed on an upper portion of the transition layer. The steep-slope field-effect transistor applies a reference potential or more to the control gate to discharge or bring in at least one charge stored in the floating gate.

Abstract: An electronic device comprises a semiconductor memory that includes: a first line; a second line disposed over the first line to be spaced apart from the first line; a variable resistance layer disposed between the first line and the second line; a selection element layer disposed between the first line and the variable resistance layer or between the second line and the variable resistance layer; and one or more electrode layers disposed over or under the selection element layer or disposed over and under the selection element layer, the one or more electrode layers being adjacent to the selection element layer, wherein each of the one or more electrode layers includes a first electrode layer and a second electrode layer, the second electrode layer including a second carbon layer containing nitrogen, the first electrode layer including a first carbon layer containing a lower concentration of nitrogen or containing no nitrogen.

Abstract: Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor storage device includes a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory. The device includes a floating gate or trapping layer for storing data as non-volatile memory, the device operating as volatile memory when power is applied to the device, and the device storing data from the volatile memory as non-volatile memory when power to the device is interrupted.

Abstract: Provided is a resistive random-access memory device, including a dielectric layer located on a substrate, a first electrode which is a column located on the dielectric layer, a second electrode covering a top surface and a sidewall of the first electrode, and a variable resistance layer sandwiched between the top surface of the first electrode and the second electrode and between the sidewall of the first electrode and the second electrode and located between the second electrode and the dielectric layer.

Abstract: A non-volatile memory device includes a plurality of word lines and a control circuit. The control circuit is configured to apply a first word line pre-pulse signal of a plurality of word line pre-pulse signals to a first group of the plurality of word lines, apply a second word line pre-pulse signal of the plurality of word line pre-pulse signals to a second group of the plurality of word lines during a pre-charge period, and apply a third word line pre-pulse signal of the plurality of word lines pre-pulse signals to a third group of the plurality of word lines during the pre-charge period. A voltage level of the second word line pre-pulse signal is greater than that of the first word line pre-pulse signal, and a voltage level of the third word line pre-pulse signal is greater than that of the second word line pre-pulse signal.

Abstract: Dense feature scale detection can be implemented using multiple convolutional neural networks trained on scale data to more accurately and efficiently match pixels between images. An input image can be used to generate multiple scaled images. The multiple scaled images are input into a feature net, which outputs feature data for the multiple scaled images. An attention net is used to generate an attention map from the input image. The attention map assigns emphasis as a soft distribution to different scales based on texture analysis. The feature data and the attention data can be combined through a multiplication process and then summed to generate dense features for comparison.

Abstract: A bit line sense circuit and a memory are disclosed in the present application. The bit line sense circuit includes: L storage unit groups, each storage unit group including H bit lines, both L and H being positive integers greater than or equal to 2; and M sense amplifier groups, configured to write or read storage data to or from the bit lines in the storage unit groups and electrically connected to the L storage unit groups, M being an integer multiple of L or L being an integer multiple of M. Two adjacent bit lines of the H bit lines are connected to the different sense amplifier groups.

Abstract: Provided are a reception apparatus, a reception system, a reception method, and a storage medium that can naturally provide a personal conversation in accordance with a user without requiring the user to register the personal information thereof in advance. A disclosure includes a face information acquisition unit that acquires face information of a user; a face matching unit that matches, against face information of one user, the face information registered in a user information database in which user information including the face information of the user and the reception information is registered; and a user information management unit that, when a result of matching of the face information performed by the face matching unit is unmatched, registers the user information of the one user to the user information database.

Abstract: A system includes one or more processors coupled to a non-transitory memory, where the one or more processors are configured to generate, using a training set comprising one or more two-dimensional (2D) training images of a dental arch and a three-dimensional (3D) dental arch model, a machine-learning model configured to generate 3D models of dental arches from 2D images of the dental arches, receive one or more 2D images of a dental arch of a user obtained by a user device of the user, and execute the machine-learning model using the one or more 2D images as input to generate a 3D model of the dental arch of the user.

Abstract: A method and apparatus for sample adaptive offset without sign coding. The method includes selecting an edge offset type for at least a portion of an image, classifying at least one pixel of at least the portion of the image into edge shape category, calculating an offset of the pixel, determining the offset is larger or smaller than a predetermined threshold, changing a sign of the offset based on the threshold determination; and performing entropy coding accounting for the sign of the offset and the value of the offset.

Abstract: Systems and methods for authenticating material samples are provided. Digital images of the samples are processed to extract computer-vision features, which are used to train a classification algorithm along with location and optional time information. The extracted features/information of a test sample are evaluated by the trained classification algorithm to identify the test sample. The results of the evaluation are used to track and locate counterfeits or authentic products.

Abstract: A motion estimation system 80 includes a pose acquisition unit 81 and an action estimation unit 82. The pose acquisition unit 81 acquires, in time series, pose information representing a posture of one person and a posture of another person identified simultaneously in a situation in which a motion of the one person affects a motion of the other person. The action estimation unit 82 divides the acquired time series pose information on each person by unsupervised learning to estimate an action series that is a series of motions including two or more pieces of pose information.

Abstract: The present invention relates to an apparatus and method for encoding and decoding an image by skip encoding. The image-encoding method by skip encoding, which performs intra-prediction, comprises: performing a filtering operation on the signal which is reconstructed prior to an encoding object signal in an encoding object image; using the filtered reconstructed signal to generate a prediction signal for the encoding object signal; setting the generated prediction signal as a reconstruction signal for the encoding object signal; and not encoding the residual signal which can be generated on the basis of the difference between the encoding object signal and the prediction signal, thereby performing skip encoding on the encoding object signal.

Abstract: Methods, systems, and devices for power gating in a memory device are described for using one or more memory cells as drivers for load circuits of a memory device. A group of memory cells of the memory device may represent memory cells that include a switching component and that omit a memory storage element. These memory cells may be coupled with respective plate lines that may be coupled with a voltage source having a first supply voltage. Each memory cell of the group may also be coupled with a respective digit line that may be coupled with the load circuits. Respective switching components of the group of memory cells may therefore act as drivers to apply the first supply voltage to one or more load circuits by coupling a digit line with a plate line having the first supply voltage.

Abstract: Methods, systems, and devices for memory device decoder configurations are described. A memory device may include an array of memory cells and decoder circuits. The array may include one or more memory cells coupled with an access line, and a decoder circuit may be configured to bias the access line to one or more voltages. The decoder circuit may include a first transistor coupled with the access line and a second transistor coupled with the access line. The first transistor may be a planar transistor having a first gate electrode formed on a substrate, and the second transistor may be a trench transistor having a second gate electrode that extends into a cavity of the substrate, where a length of a first gate electrode may be greater than a length of the second gate electrode.

Abstract: A method (of reading a ferroelectric field-effect transistor (FeFET) configured as a 2-bit storage device that stores two bits, wherein the FeFET includes a first source/drain (S/D) terminal, a second S/D terminal, a gate terminal and a ferroelectric layer, a second bit being at a first end of the ferroelectric layer, the first end being proximal to the first S/D terminal) includes reading the second bit including: applying a gate sub-threshold voltage to the gate terminal; applying a read voltage to the second S/D terminal; applying a do-not-disturb voltage to the first S/D terminal; and sensing a first current at the second S/D terminal; and wherein the read voltage is lower than the do-not-disturb voltage.

Abstract: A method for fabricating an electronic device including a semiconductor memory including one or more memory elements, includes: forming a first insulating layer; forming a diffusion barrier layer over the first insulating layer; forming a second insulating layer over the diffusion barrier layer, the second insulating layer and the first insulating layer being formed of a common insulating material; doping one of a first dopant and a second dopant in the first insulating layer to form a selection element layer when the first dopant is doped or to form a variable resistance layer when the second dopant is doped; and doping the other one of the first dopant and the second dopant in the second insulating layer.