Abstract: A semiconductor memory, comprising a negative voltage providing unit, which is used for providing a first negative voltage to a word line during a read operation, and comprises: a clamping unit that comprises an input end, a control end and an output end, wherein the input end is coupled to a common ground end of the memory, and the control end is used for receiving a first signal; an energy storage capacitor, a first end of which is coupled to the output end, and a second end that is used for receiving a second signal; and a negative voltage providing end which is coupled to the first end, wherein the clamping unit is used for: pulling the voltage at the output end to the voltage at the input end when the first signal is “0”; and clamping the output end at a clamping voltage when the first signal is “1”.

Abstract: A complementary metal oxide semiconductor (CMOS) circuit of a memory device includes a high-voltage functional circuit and an auxiliary clamping circuit. The high-voltage functional circuit includes at least one MOS transistor. One of a source terminal and a drain terminal of an MOS transistor is coupled to an input high-voltage. The high-voltage functional circuit has an output voltage that, when an enable signal is valid, gradually increases and reaches a maximum value. The auxiliary clamping circuit is arranged between the input high-voltage and the one of the source terminal and the drain terminal of the MOS transistor, and is configured to clamp the voltage input to the one of the source terminal and the drain terminal of the MOS transistor during a rising phase of the output voltage, so that the clamping voltage is smaller than the input high-voltage.

Abstract: An electronic chip includes at least a first array of first elementary cells and a second array of second elementary cells. The first and second elementary cells form two types of phase change memory having a storage element formed by a volume of phase change material having either a crystalline state or an amorphous state depending on the bit stored. Each first elementary cell includes a volume of a first phase change material, and each second elementary cell includes a volume of a second phase change material that is different from the first material. Each elementary cell includes a heating connector configured for the passage of a heating current adapted to cause a phase change of the volume of phase change material of the elementary cell.

Abstract: A three-dimensional data encoding method of encoding three-dimensional points includes: re-ordering, in a re-ordered data order, pieces of attribute information of the three-dimensional points arranged in a predetermined order; encoding the pieces of attribute information re-ordered in the re-ordering, in accordance with the re-ordered data order; and generating a bitstream including (i) order information indicating the predetermined order and (ii) the pieces of attribute information encoded in the encoding.

Abstract: Provided herein may be a memory device and a method of operating the same. The memory device may include a plurality of memory cells, a program operation performer configured to perform a plurality of program loops on the plurality of memory cells, a step voltage calculator configured to calculate a step voltage, the step voltage being a difference of magnitude between program voltages that are applied in any two consecutive program loops, a reference bit determiner configured to determine a reference number of fail bits based on a magnitude of the step voltage, and a verification result generator configured to generate verification result information based on a result of a comparison between the reference number of fail bits and a number of on-cells, among the plurality of memory cells, identified in a verify operation that is included in a program loop, among the plurality of program loops.

Abstract: Systems and methods are provided for receiving at least one image and a reference image, and performing a plurality of downscaling operations having separable convolutions on the received at least one image. A plurality of residual blocks may be formed, with each residual block containing two separable convolutions of the kernel and two instance normalizations. A plurality of upscaling operations may be performed on the plurality of residual blocks, and a stylized image may be displayed based on at least the performed plurality of upscaling operations and the reference image.

Abstract: The present technology is directed to identifying and labeling a vehicle appendage. More specifically, the present technology is generally related to receiving one or more lidar points associated with a vehicle having an appendage and outputting a label to classify the vehicle and the appendage. In some examples, a first portion of the one or more lidar points associated with the vehicle having the appendage represents the vehicle and a second portion of the one or more lidar points associated with the vehicle having the appendage represents the appendage The present disclosure can further train a perception model to output the label to classify the vehicle and the appendage.

Abstract: In an embodiment, a memory circuit includes: a memory, N latch circuits coupled in parallel, a data multiplexer, a logic circuit, and a data path data path. The memory array is configured to provide read data to a first data bus, and each latch circuit is configured to store read data from the first data bus. The data multiplexer has N data inputs respectively coupled to data outputs of the N latch circuits and is configured to select a data input of the N data inputs of the data multiplexer to connect to the data output of the data multiplexer based on a selection input of the data multiplexer. The data path is configured to cause a propagation of data from a data output of the data multiplexer to a data input of the logic circuit.

Abstract: Multi-port semiconductor memory cells including a common floating body region configured to be charged to a level indicative of a memory state of the memory cell. The multi-port semiconductor memory cells include a plurality of gates and conductive regions interfacing with said floating body region. Arrays of memory cells and method of operating said memory arrays are disclosed for making a memory device.

Abstract: The present disclosure relates to systems, methods, and non-transitory computer readable media for accurately and flexibly generating harmonized digital images utilizing an object-to-object harmonization neural network. For example, the disclosed systems implement, and learn parameters for, an object-to-object harmonization neural network to combine a style code from a reference object with features extracted from a target object. Indeed, the disclosed systems extract a style code from a reference object utilizing a style encoder neural network. In addition, the disclosed systems generate a harmonized target object by applying the style code of the reference object to a target object utilizing an object-to-object harmonization neural network.

Abstract: The present disclosure is drawn to, among other things, an antifuse circuit. The antifuse circuit includes a plurality of antifuse bitcells and a reference resistor. Each antifuse bitcell includes two or more memory bits and a reference resistor. The two or more memory bits are configured to be in a programmed state and at least one unprogrammed state.

Abstract: Systems and methods are disclosed for fused processing of a continuous mathematical operator. Fused processing of continuous mathematical operations, such as pointwise non-linear functions without storing intermediate results to memory improves performance when the memory bus bandwidth is limited. In an embodiment, a continuous mathematical operation including at least two of convolution, upsampling, pointwise non-linear function, and downsampling is executed to process input data and generate alias-free output data. In an embodiment, the input data is spatially tiled for processing in parallel such that the intermediate results generated during processing of the input data for each tile may be stored in a shared memory within the processor. Storing the intermediate data in the shared memory improves performance compared with storing the intermediate data to the external memory and loading the intermediate data from the external memory.

Abstract: Techniques are disclosed for training and applying a denoising model. The denoising model includes multiple specialized denoisers and a generalizer, each of which is a machine learning model. The specialized denoisers are trained to denoise images associated with specific ranges of noise parameters. The generalizer is trained to generate per-pixel denoising kernels for denoising images associated with arbitrary noise parameters using outputs of the specialized denoisers. Subsequent to training, a noisy image, such as a live-action image or a rendered image, can be denoised by inputting the noisy image into the specialized denoisers to obtain intermediate denoised images that are then input, along with the noisy image, into the generalizer to obtain per-pixel denoising kernels, which can be normalized and applied to denoise the noisy image.

Abstract: A semiconductor device with a small circuit area and low power consumption is provided. The semiconductor device includes first to fourth cells, a current mirror circuit, and first to fourth wirings, and the first to fourth cells each include a first transistor, a second transistor, and a capacitor. In each of the first to fourth cells, a first terminal of the first transistor is electrically connected to a first terminal of the capacitor and a gate of the second transistor. The first wiring is electrically connected to first terminals of the second transistors in the first cell and the second cell, the second wiring is electrically connected to first terminals of the second transistors in the third cell and the fourth cell, the third wiring is electrically connected to second terminals of the capacitors in the first cell and the third cell, and the fourth wiring is electrically connected to second terminals of the capacitors in the second cell and the fourth cell.

Abstract: Systems and methods for image processing are described. The systems and methods include receiving a low-resolution image; generating a feature map based on the low-resolution image using an encoder of a student network, wherein the encoder of the student network is trained based on comparing a predicted feature map from the encoder of the student network and a fused feature map from a teacher network, and wherein the fused feature map represents a combination of first feature map from a high-resolution encoder of the teacher network and a second feature map from a low-resolution encoder of the teacher network; and decoding the feature map to obtain prediction information for the low-resolution image.

Abstract: A memory device may include at least one multinary memory cell. Each multinary memory cell includes a parallel connection of N sub-bit units. N is an integer greater than 1. Each of the N sub-bit units includes a series connection of a respective transistor and a respective capacitor. A first sub-bit unit includes a first capacitor having a capacitance of C, and each i-th sub-unit includes an i-th capacitor having a capacitance of about 2i-1×C. A multinary bit having 2N values may be stored. A device network including multiple multinary logic units is also provided. Each of multiple multinary logic unit includes a parallel connection of N sub-bit units. Each sub-bit unit includes a series connection of a respective transistor and a respective capacitor having capacitance ratios of powers of 2.

Abstract: A semiconductor memory device includes a memory string, a voltage supply circuit, a plurality of control signal lines, a row decoder, and a control circuit. The voltage supply circuit is configured to generate a plurality of operation voltages to operate the semiconductor memory device. The operation voltages include a negative voltage. The plurality of control signal lines is connected between the voltage supply circuit and the memory string. The row decoder includes a plurality of transistors provided in the plurality of control signal lines, respectively. The control circuit is configured to control the transistors of the row decoder, and cause the negative voltage to be supplied to the row decoder during a certain period of time in which a voltage of one of the control signal lines drops to a negative level.

Abstract: A gait analysis apparatus 10 includes, a data acquisition unit 11 that acquires a three-dimensional point cloud data of a human to be analyzed, a center of gravity location calculation unit 12 that calculates coordinates of a center of gravity location on the three-dimensional point cloud data of the human to be analyzed by using coordinates of each point constituting the acquired three-dimensional point cloud data, and a gait index calculation unit 13 that calculates a gait index of the human to be analyzed by using the calculated center of gravity location.

Abstract: A system for reconstructing a magnetic particle image based on a pre-trained model aims to address the influence by point spread function and reduce the computational and time costs, which results in low reconstruction accuracy, or high acquisition time and computational costs for high-precision images. The system is implemented by: generating a simulation system matrix; pre-training a pre-constructed neural network model, and fine-tuning a pre-trained neural network model by performing a downstream task; and inputting real data corresponding to the downstream task into the pre-trained neural network model after fine-tuning, thereby playing an auxiliary role to acquire a high-quality reconstructed MPI image. The system fits the relationship between different harmonics, which helps enhance frequency-domain information.

Abstract: A dual watermarking method for trajectory data based on robust watermarking and fragile watermarking uses an encryption algorithm to construct robust watermark information, and then a farthest pair of feature points in a minimum convex hull of is set as constant points. Further quantization index modulation technology is used to embed robust watermark information into angles constructed from feature points and constant points. Finally, the angles and distance ratios constructed by trajectory points and constant points are used to group trajectory points. Within each group, spatiotemporal attributes of the trajectory points are taken as fragile watermark bits to be embedded in the distance ratios constructed by the trajectory points. A process of watermark detection is consistent with the embedding of watermark information. Watermarks embedded in the trajectory data based on the dual watermarking method have high robustness against translation, rotation, and scaling attacks.