Abstract: An image processing apparatus includes an image acquisition unit configured to acquire a plurality of temporally different images each of which has degraded by a turbulence, a parameter acquisition unit configured to acquire a learned network parameter, and a measurement unit configured to measure a turbulence strength from the plurality of images using the network parameter and a neural network.

Abstract: Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor storage device includes a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory. The device includes a floating gate or trapping layer for storing data as non-volatile memory, the device operating as volatile memory when power is applied to the device, and the device storing data from the volatile memory as non-volatile memory when power to the device is interrupted.

Abstract: An integrated circuit device includes a plurality of memory cells each including a channel region, a first sub-word line, a second sub-word line, and a storage element. A word line driving circuit is configured to drive the first and sub-word lines. The word line driving circuit includes a PMOS transistor, an NMOS transistor, a keeping NMOS transistor, and a first keeping PMOS transistor. A negative voltage is applied to a source of the NMOS transistor, the negative voltage is applied to a source of the keeping NMOS transistor, the first sub-word line is connected to a source of the first keeping PMOS transistor, the second sub-word line is connected to a drain of the first keeping PMOS transistor, and a negative voltage is applied to a gate of the first keeping PMOS transistor.

Abstract: Where an event is determined to have occurred at a location within a vicinity of a plurality of actors, imaging data captured using cameras having the location is processed using one or more machine learning systems or techniques operating on the cameras to determine which of the actors is most likely associated with the event. For each relevant pixel of each image captured by a camera, the camera returns a set of vectors extending to pixels of body parts of actors who are most likely to have been involved with an event occurring at the relevant pixel, along with a measure of confidence in the respective vectors. A server receives the vectors from the cameras, determines which of the images depicted the event in a favorable view, based at least in part on the quality of such images, and selects one of the actors as associated with the event accordingly.

Abstract: A memory is provided which comprises a capacitor including non-linear polar material. The capacitor may have a first terminal coupled to a node (e.g., a storage node) and a second terminal coupled to a plate-line. The capacitors can be a planar capacitor or non-planar capacitor (also known as pillar capacitor). The memory includes a transistor coupled to the node and a bit-line, wherein the transistor is controllable by a word-line, wherein the plate-line is parallel to the bit-line. The memory includes a refresh circuitry to refresh charge on the capacitor periodically or at a predetermined time. The refresh circuit can utilize one or more of the endurance mechanisms. When the plate-line is parallel to the bit-line, a specific read and write scheme may be used to reduce the disturb voltage for unselected bit-cells. A different scheme is used when the plate-line is parallel to the word-line.

Abstract: A Static Random Access Memory (SRAM) cell that may include a first pull-up transistor, a second pull-up transistor, a first pull-down transistor, a second pull-down transistor, a first pass-gate transistor and a second pass-gate transistor provided at two levels on a substrate. The respective transistors may be vertical transistors. The first pull-up transistor and the second pull-up transistor may be provided at a first level, and the first pull-down transistor, the second pull-down transistor, the first pass-gate transistor and the second pass-gate transistor may be provided at a second level different from the first level. A region where the first pull-up transistor and the second pull-up transistor are located and a region where the first pull-down transistor, the second pull-down transistor, the first pass-gate transistor and the second pass-gate transistor are located may at least partially overlap in a vertical direction with respect to an upper surface of the substrate.

Abstract: Provided is a method of displaying price tag information applied to a price tag generating apparatus in a shelf system which includes a shelf and at least one display screen arranged on the shelf. The method includes: acquiring an image of a commodity placed on the shelf; determining price tag related information based on the image of the commodity, wherein the price tag related information comprises price tag information of the commodity; and sending the price tag related information to a target display screen, which is a display screen for displaying the price tag information in the at least one display screen, and the price tag related information being configured to allow the target display screen to display the price tag information.

Abstract: The invention provides a semiconductor layout pattern, the semiconductor layout pattern includes a substrate, a plurality of ternary content addressable memories (TCAM) are arranged on the substrate, the layout of at least two TCAM is mirror symmetric with each other along an axis of symmetry, and the two TCAM are connected to the same search line (SL) together.

Abstract: According to one embodiment, a magnetoresistive memory device includes: a first conductor; a layer stack; an insulator on a side surface of the layer stack; a second conductor on a second surface of the layer stack; a third conductor; and a fourth conductor on the third conductor. The layer stack includes a first ferromagnetic layer, a second ferromagnetic layer, and an insulating layer between the first ferromagnetic layer and the second ferromagnetic layer and has a first surface in contact with the first conductor. The second surface is at an opposite side of the first surface. The third conductor has a portion on the second conductor and a portion on a side surface of the insulator.

Abstract: An integrated circuit includes: a first wiring layer on which a first bit line pattern and a positive power supply pattern, a first power supply line landing pad, and a first word line landing pad are formed; a second wiring layer on which a first negative power supply pattern connected to the first power supply line landing pad, and a first word line pattern connected to the first word line landing pad are formed; a third wiring layer on which a second negative power supply pattern connected to the first negative power supply pattern, and a second word line landing pad connected to the first word line pattern are formed; and a fourth wiring layer on which a second word line pattern, connected to the second word line landing pad, are formed.

Abstract: An ECU includes a memory including computer executable instructions for monitoring the condition of a ground engaging tool, and a processor coupled to the memory and configured to execute the computer executable instructions, the computer executable instructions when executed by the processor cause the processor to: acquire an image of the ground engaging tool, evaluate the image using an algorithm that compares the acquired image to a database of existing images to determine the damage, the amount of wear, or the absence of the ground engaging tool, and grade the quality of the acquired image.

Abstract: Where an event is determined to have occurred at a location within a vicinity of a plurality of actors, imaging data captured using cameras having the location is processed using one or more machine learning systems or techniques operating on the cameras to determine which of the actors is most likely associated with the event. For each relevant pixel of each image captured by a camera, the camera returns a set of vectors extending to pixels of body parts of actors who are most likely to have been involved with an event occurring at the relevant pixel, along with a measure of confidence in the respective vectors. A server receives the vectors from the cameras, determines which of the images depicted the event in a favorable view, based at least in part on the quality of such images, and selects one of the actors as associated with the event accordingly.

Abstract: Where an event is determined to have occurred at a location within a vicinity of a plurality of actors, imaging data captured using cameras having the location is processed using one or more machine learning systems or techniques operating on the cameras to determine which of the actors is most likely associated with the event. For each relevant pixel of each image captured by a camera, the camera returns a set of vectors extending to pixels of body parts of actors who are most likely to have been involved with an event occurring at the relevant pixel, along with a measure of confidence in the respective vectors. A server receives the sets of vectors from the cameras, determines which of the images depicted the event in a favorable view, based at least in part on the quality of such images, and selects one of the actors as associated with the event accordingly.

Abstract: There is provided a method for generating a personalized Head Related Transfer Function (HRTF). The method can include capturing an image of an ear using a portable device, auto-scaling the captured image to determine physical geometries of the ear and obtaining a personalized HRTF based on the determined physical geometries of the ear.

Abstract: The various embodiments of the present invention relate to an electronic apparatus, and a method for controlling same. The electronic apparatus according to the present invention comprises a display, a communication module, and a processor electrically connected to the display and communication module, wherein the processor controls so that an object detected in an image displayed on the display is recognized, and one or more elements contained in the object are classified and displayed on the display, and can control so that an image similar to the detected object is searched for, by means of the communication module, and displayed on the display.

Abstract: Provided is a magnetic storage element including a stack structure which includes a fixed layer whose magnetization direction is fixed, a storage layer whose magnetization direction is reversible, and a non-magnetic layer sandwiched between the fixed layer and the storage layer. The magnetization direction has a direction along a stack direction of the stack structure, and the fixed layer or the storage layer has a region which contains at least one contained element selected from the element group consisting of B, C, N, Al, Mg, and Si at 30 atm % or more and 80 atm % or less.

Abstract: A magnetic device may include a layer stack including a work function structure, a dielectric layer, and a ferromagnetic layer, where the ferromagnetic layer is positioned between the work function structure and the dielectric layer. The work function structure is configured to deplete electrons from the ferromagnetic layer or accumulate electrons in the ferromagnetic layer. A magnetization orientation of the ferromagnetic layer is configured to be switched by a voltage applied across the layer stack or by a voltage applied across or through the work function structure.

Abstract: A circuit may include a low-voltage flash memory integrated with a vertical field effect transistor and a non-volatile memory element. The low-voltage flash memory may be coupled to the non-volatile memory element by the vertical field effect transistor, one or more bit-lines, and one or more word-lines. The low-voltage flash memory may provide a lower significance conductance and the non-volatile memory element may provide a higher significance conductance. The low-voltage flash memory may include a source and a drain. The source may be separated from the drain by an epitaxial channel. The low-voltage flash memory may include a floating gate. The floating gate may be separated from the epitaxial channel by a first dielectric layer. The low-voltage flash memory may include a control gate. The control gate may be separated from the floating gate by a second dielectric layer.

Abstract: Provided are a three-dimensional semiconductor memory device, a method for manufacturing the same, a method for operating the same, and an electronic system including the same. The three-dimensional semiconductor memory device includes a substrate, a stack structure on the substrate, and vertical channel structures, which are provided in channel holes penetrating the stack structure, wherein each of the vertical channel structures includes a data storage pattern, a vertical channel pattern, a conductive pad, and a vertical semiconductor pattern, wherein the vertical channel pattern includes a first portion contacting the upper surface of the substrate and a second portion provided between the data storage pattern and the vertical semiconductor pattern, and wherein the vertical semiconductor pattern is spaced apart from the substrate with the first portion of the vertical channel pattern therebetween.

Abstract: Some embodiments include an integrated assembly having a primary access transistor. The primary access transistor has a first source/drain region and a second source/drain region. The first and second source/drain regions are coupled to one another when the primary access transistor is in an ON mode, and are not coupled to one another when the primary access transistor is in an OFF mode. A charge-storage device is coupled with the first source/drain region. A digit line is coupled with the second source/drain region through a secondary access device. The secondary access device has an ON mode and an OFF mode. The digit line is coupled with the charge-storage device only when both the primary access transistor and the secondary access device are in their respective ON modes.