Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.

Abstract: A phase change memory (PCM) cell comprises a first electrode comprised of a first electrically conductive material, a second electrode comprised of a second electrically conductive material, a first phase change layer positioned between the first electrode and the second electrode and being comprised of a first phase change material, and a second phase change layer positioned between the first electrode and the second electrode and being comprised of a second phase change material. The first phase change material has a first resistivity, the second phase change material has a second resistivity, and wherein the first resistivity is at least two times the second resistivity.

Abstract: The present disclosure describes a method, an apparatus, and a storage medium for recognizing an obstacle. The method includes acquiring, by a device, point cloud data obtained by scanning surroundings of a target vehicle by a sensor in the target vehicle. The device includes a memory storing instructions and a processor in communication with the memory. The method further includes converting, by the device, the point cloud data into a first image used for showing the surroundings; and recognizing, by the device, from the first image, a first object in the surroundings as an obstacle through a first neural network model.

Abstract: A memory device includes an open-for-contact region located between the memory blocks, and a row decoder disposed between global lines to which an operating voltage is supplied and the local lines and configured to transfer the operating voltage to one memory block among the memory blocks in response to a row address, wherein a plurality of contacts are formed in the open-for-contact region and configured to transmit a voltage between the bit lines and a peripheral circuit, wherein a dummy region is included in the row decoder and disposed paced apart from the open-for-contact region in the second direction, and wherein a discharge switch is included in the dummy region and configured to discharge the global lines in response to a discharge signal.

Abstract: A system and method for reconstructing an image of a target object using an iterative reconstruction technique can include a machine learning model as a regularization filter (100). An image data set for a target object generated using an imaging modality can be received, and an image of the target object can be reconstructed using an iterative reconstruction technique that includes a machine learning model as a regularization filter (100) used in part to reconstruct the image of the target object. The machine learning model can be trained prior to receiving the image data using learning datasets that have image data associated with the target object, where the learning datasets providing objective data for training the machine learning model, and the machine learning model can be included in the iterative reconstruction technique to introduce the object features into the image of the target object being reconstructed.

Abstract: A computer implemented method for determining an entry of an occupancy map of a vicinity of a vehicle comprises the following steps carried out by computer hardware components: acquiring first sensor data of a first sensor of the vicinity of the vehicle; acquiring second sensor data of a second sensor of the vicinity of the vehicle; determining a first sensor data portion of the first sensor data which corresponds to a potential object in the vicinity of the vehicle; based on the first sensor data portion, determining a second sensor data portion of the second sensor data which corresponds to a location of the potential object; and determining an entry of the occupancy map based on the first sensor data portion and the second sensor data portion.

Abstract: The present application discloses a method and an apparatus for detecting wearing of a safety helmet, a device and a storage medium. The method for detecting wearing of a safety helmet includes: acquiring a first image collected by a camera device, where the first image includes at least one human body image; determining the at least one human body image and at least one head image in the first image; determining a human body image corresponding to each head image in the at least one human body image according to an area where the at least one human body image is located and an area where the at least one head image is located; and processing the human body image corresponding to the at least one head image according to a type of the at least one head image.

Abstract: A memory is provided which comprises a capacitor including non-linear polar material. The capacitor may have a first terminal coupled to a node (e.g., a storage node) and a second terminal coupled to a plate-line. The capacitors can be a planar capacitor or non-planar capacitor (also known as pillar capacitor). The memory includes a transistor coupled to the node and a bit-line, wherein the transistor is controllable by a word-line, wherein the plate-line is parallel to the bit-line. The memory includes a refresh circuitry to refresh charge on the capacitor periodically or at a predetermined time. The refresh circuit can utilize one or more of the endurance mechanisms. When the plate-line is parallel to the bit-line, a specific read and write scheme may be used to reduce the disturb voltage for unselected bit-cells. A different scheme is used when the plate-line is parallel to the word-line.

Abstract: A memory is provided which comprises a capacitor including non-linear polar material. The capacitor may have a first terminal coupled to a node (e.g., a storage node) and a second terminal coupled to a plate-line. The capacitors can be a planar capacitor or non-planar capacitor (also known as pillar capacitor). The memory includes a transistor coupled to the node and a bit-line, wherein the transistor is controllable by a word-line, wherein the plate-line is parallel to the bit-line. The memory includes a refresh circuitry to refresh charge on the capacitor periodically or at a predetermined time. The refresh circuit can utilize one or more of the endurance mechanisms. When the plate-line is parallel to the bit-line, a specific read and write scheme may be used to reduce the disturb voltage for unselected bit-cells. A different scheme is used when the plate-line is parallel to the word-line.

Abstract: A system configured to receive video and/or images from an image capture device over a livestock path, generate feature maps from an image of the video by applying at least a first convolutional neural network, slide a window across the feature maps to obtain a plurality of anchor shapes, determine if each anchor shape contains an object to generate a plurality of regions of interest, each of the plurality of regions of interest being a non-rectangular, polygonal shape, extract feature maps from each region of interest, classify objects in each region of interest, in parallel with classification, predict segmentation masks on at least a subset of the regions of interest in a pixel-to-pixel manner, identify individual animals within the objects based on classifications and the segmentation masks, and count individual animals based on identification, and provide the count to a digital device for display, processing, and/or reporting.

Abstract: Disclosed herein is an apparatus that includes a plurality of memory sections each including a plurality of word lines, a predecoder circuit configured to generate predecoded section address signals to select one of the plurality of memory sections and predecoded word line address signals to select one of the word lines included in a selected one of the plurality of memory sections based on a row address, and a section address control circuit configured to retain the predecoded section address signals regardless of an update of the row address in a test operation mode.

Abstract: A memory is provided which comprises a capacitor including non-linear polar material. The capacitor may have a first terminal coupled to a node (e.g., a storage node) and a second terminal coupled to a plate-line. The capacitors can be a planar capacitor or non-planar capacitor (also known as pillar capacitor). The memory includes a transistor coupled to the node and a bit-line, wherein the transistor is controllable by a word-line, wherein the plate-line is parallel to the bit-line. The memory includes a refresh circuitry to refresh charge on the capacitor periodically or at a predetermined time. The refresh circuit can utilize one or more of the endurance mechanisms. When the plate-line is parallel to the bit-line, a specific read and write scheme may be used to reduce the disturb voltage for unselected bit-cells. A different scheme is used when the plate-line is parallel to the word-line.

Abstract: Structures for 3D sense amplifiers for 3D memories are disclosed. A first embodiment uses one type of vertical transistors in constructing 3D sense amplifiers. A second embodiment uses both n- and p-type transistors for 3D sense amplifiers. Either or both of n- and p-type transistors are vertical transistors. The n- and p-type transistors may reside on different levels, or on the same level above a substrate if both are vertical transistors. In any embodiment, different options are available for gate contact formation. In any embodiments and options or alternatives thereof, one or more sense-enable circuits may be used. Sense amplifiers for several bit lines may be staggered on one or both sides of a memory array. Column multiplexers may be used to couple particular bit lines to data outputs. Bit-line multiplexers may be used to couple certain bit lines to shared 3D sense amplifiers.

Abstract: A method is provided for generating a personalized Head Related Transfer Function (HRTF). The method can include capturing an image of an ear using a portable device, auto-scaling the captured image to determine physical geometries of the ear and obtaining a personalized HRTF based on the determined physical geometries of the ear. In addition, a system and a method in association with the system are also provided for customizing audio experience. Customization of audio experience can be based on derivation of at least one customized audio response characteristic which can be applied to an audio device used by a person. Finally, methods and systems are provided for rendering audio over headphones with head tracking enabled by, for example, exploiting efficiencies in creating databases and filters for use in filtering 3D audio sources for more realistic audio rendering and also allowing greater head movement to enhance the spatial audio perception.

Abstract: A novel interpretable and steerable deep sequence modeling technique is disclosed. The technique combines prototype learning and RNNs to achieve both interpretability and high accuracy. Experiments and case studies on different real-world sequence prediction/classification tasks demonstrate that the model is not only as accurate as other state-of-the-art machine learning techniques but also much more interpretable. In addition, a large-scale user study on Amazon Mechanical Turk demonstrates that for familiar domains like sentiment analysis on texts, the model is able to select high quality prototypes that are well aligned with human knowledge for prediction and interpretation. Furthermore, the model obtains better interpretability without a loss of performance by incorporating the feedback from a user study to update the prototypes, demonstrating the benefits of involving human-in-the-loop for interpretable machine learning.

Abstract: Described are systems and methods for providing power loss immunity in memory programming operations. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines; and a controller coupled to the memory array, the controller to perform operations comprising: causing a programming pulse to be applied to to one or more wordlines of the memory array; responsive to determining that a threshold voltage of one or more memory cells of the memory array has reached a pre-program verify level, causing a first bias voltage level to be applied to a first subset of bitlines of the memory array and causing a second bias voltage level to be applied to a second subset of bitlines of the memory array.

Abstract: Fast and scalable architectures and methods adaptable to available resources, that (1) compute 2-D convolutions using 1-D convolutions, (2) provide fast transposition and accumulation of results for computing fast cross-correlations or 2-D convolutions, and (3) provide parallel computations using pipelined 1-D convolvers. Additionally, fast and scalable architectures and methods that compute 2-D linear convolutions using Discrete Periodic Radon Transforms (DPRTs) including the use of scalable DPRT, Fast DPRT, and fast 1-D convolutions.

Abstract: A processing device of a memory sub-system is configured to identify a read level of a plurality of read levels associated with a voltage bin of a plurality of voltage bins of a memory device; assign a first threshold voltage offset to the read level of the voltage bin; assign a second threshold voltage offset to the read level of the voltage bin; perform, on block associated with the read level, a first operation of a first operation type using the first threshold voltage offset; and perform, on the blocks associated with the read level, a second operation of a second operation type using the second threshold voltage offset.

Abstract: A process for drilling a well into a subsurface formation includes receiving data representing depth maps for a given subsurface region, each depth map being generated from seismic data acquired in a seismic survey at a subsurface region. The process includes determining, for depth maps of the plurality, respective weight values; generating data representing a combination of the depth maps based on the respective weight values; generating a cumulative distribution function (CDF) for a particular location in the subsurface region based on the data representing a combination of the depth maps; determining, based on the CDF for that particular location, a probability value representing a depth at which a geological layer occurs in the subsurface region at the particular location; and drilling the well into the subsurface formation at the particular location to a target depth based on the probability value.

Abstract: A device includes an electronic component, and the electronic component includes a first pad, a second pad, and a strip connecting the first pad and the second pad. The device further includes a first electrode in contact with the first pad and a second electrode in contact with the second pad. The electronic component is made of a phase change material. At least one of the first electrode and the second electrode is coated with a material that is configured to increase a difference in workfunction between the first electrode and the second electrode.