Abstract: Fast and scalable architectures and methods adaptable to available resources, that (1) compute 2-D convolutions using 1-D convolutions, (2) provide fast transposition and accumulation of results for computing fast cross-correlations or 2-D convolutions, and (3) provide parallel computations using pipelined 1-D convolvers. Additionally, fast and scalable architectures and methods that compute 2-D linear convolutions using Discrete Periodic Radon Transforms (DPRTs) including the use of scalable DPRT, Fast DPRT, and fast 1-D convolutions.

Abstract: A processing device of a memory sub-system is configured to identify a read level of a plurality of read levels associated with a voltage bin of a plurality of voltage bins of a memory device; assign a first threshold voltage offset to the read level of the voltage bin; assign a second threshold voltage offset to the read level of the voltage bin; perform, on block associated with the read level, a first operation of a first operation type using the first threshold voltage offset; and perform, on the blocks associated with the read level, a second operation of a second operation type using the second threshold voltage offset.

Abstract: A process for drilling a well into a subsurface formation includes receiving data representing depth maps for a given subsurface region, each depth map being generated from seismic data acquired in a seismic survey at a subsurface region. The process includes determining, for depth maps of the plurality, respective weight values; generating data representing a combination of the depth maps based on the respective weight values; generating a cumulative distribution function (CDF) for a particular location in the subsurface region based on the data representing a combination of the depth maps; determining, based on the CDF for that particular location, a probability value representing a depth at which a geological layer occurs in the subsurface region at the particular location; and drilling the well into the subsurface formation at the particular location to a target depth based on the probability value.

Abstract: A device includes an electronic component, and the electronic component includes a first pad, a second pad, and a strip connecting the first pad and the second pad. The device further includes a first electrode in contact with the first pad and a second electrode in contact with the second pad. The electronic component is made of a phase change material. At least one of the first electrode and the second electrode is coated with a material that is configured to increase a difference in workfunction between the first electrode and the second electrode.

Abstract: A system for updating a descriptor trail using artificial intelligence. The system is configured to display on a graphical user interface operating on a processor connected to a memory an element of diagnostic data. The system is configured to receive from a user client device an element of user constitutional data. The system is configured to display on a graphical user interface the element of user constitutional data. The system is configured to prompt an advisor input on a graphical user interface. The system is configured to receive from an advisor client device an advisor input containing an element of advisory data. The system is configured to generate an updated descriptor trail as a function of the advisor input. The system is configured to display the updated descriptor trail on a graphical user interface.

Abstract: A semiconductor memory device and a memory system are provided. The semiconductor memory device includes a fingerprint read signal generator configured to generate a fingerprint read signal in response to a refresh counting control signal, a memory cell array comprising a plurality of sub memory cell array blocks, a fingerprint output unit configured to receive data output from memory cells connected to one selected among a plurality of word lines and one selected among a plurality of bit lines of one among the plurality of sub memory cell array blocks in response to the fingerprint read signal to generate fingerprint data, and a pseudorandom number generator configured to perform a linear feedback shifting operation in response to an active command to generate sequence data, receive the fingerprint data in response to the fingerprint read signal, and generate the sequence data based on the fingerprint data.

Abstract: Apparatuses and methods for writing data to a memory array are disclosed. When data is duplicative across multiple data lines, data may be transferred across a single line of a bus rather than driving the duplicative data across all of the data lines. The data from the single data line may be provided to the write amplifiers of the additional data lines to provide the data from all of the data lines to be written to the memory. In some examples, error correction may be performed on data from the single data line rather than all of the data lines.

Abstract: A method and an electronic device for determining a presence of an obstacle in a surrounding area of a self-driving car (SDC) are provided. The method comprises receiving sensor data representative of the surrounding area of the SDC in a form of 3D point cloud data; generating, by an MLA, based on the 3D point cloud data, a set of feature vectors representative of the surrounding area; generating, by the MLA, a grid representation of the surrounding area, each given cell of the grid representation including a predicted distance parameter indicative of a distance from the given cell to a closest cell with the obstacle; and using, by the electronic device, the distance parameter to determine presence of the obstacle in the surrounding area of the SDC.

Abstract: A device, a memory interface device, and a method of implementing an active inductor circuit are disclosed. In one aspect, the device includes one or more active inductor circuits, each including a first metal-oxide-semiconductor (MOS) transistor and a second MOS transistor. The first MOS transistor has a first terminal connected to a first voltage level, a second terminal connected to a resistor, and a gate terminal. The second MOS transistor has a first terminal connected to the first voltage level, a second terminal connected to a first current source and the gate terminal of the first MOS transistor, and a gate terminal connected to the resistor and to a capacitor connected to a second voltage level. One of the first MOS transistor and the second MOS transistor is a p-channel MOS (PMOS) transistor, and another of the first MOS transistor and the second MOS transistor is an n-channel MOS (NMOS) transistor.

Abstract: A semiconductor memory device and a memory system are provided. The semiconductor memory device includes a memory cell array, a normal refresh row address generator, a hammer refresh row address generator, a refresh selection signal generator, and a selector. The normal and hammer refresh row address generators generates a normal refresh row address and a hammer refresh row address, respectively, in response to a refresh counting control signal. The refresh selection signal generator sequentially generates normal and hammer refresh selection signals in response to the refresh counting control signal. The selector selects the normal refresh row address or the hammer refresh row address in response to the normal and hammer refresh selection signals. A normal refresh operation and a hammer refresh operation are sequentially performed on a memory cell array block among plural memory cell array blocks in response to the refresh row address.

Abstract: An inspection apparatus including: a display device; and one or a plurality of processors, wherein the one or the plurality of processors is programmed to execute a method including: converting an inspection target image representing an inspection target into a virtual good article image by using a learning model, the learning model being trained so that an image representing a good article is generated based on features of a plurality of targets that are determined as good articles, generating a difference between the virtual good article image and the inspection target image as a defect candidate image, and displaying the defect candidate image on the display device.

Abstract: There is provided a magnetoresistance effect element includes: a channel layer that extends in a first direction; a recording layer which includes a film formed from a ferromagnetic material, of which a magnetization state is changed to one of two or greater magnetization states, and which is formed on the channel layer; a non-magnetic layer that is provided on a surface of the recording layer; a reference layer which is provided on a surface of the non-magnetic layer, which includes a film formed from a ferromagnetic material, and of which a magnetization direction is fixed; a terminal pair that includes a first terminal and a second terminal which are electrically connected to the channel layer with an interval in the first direction, and to which a current pulse for bringing the recording layer to any one magnetization state with a plurality of pulses is input by flowing a current to the channel layer between the first terminal and the second terminal; and a third terminal that is electrically connected to

Abstract: Three-dimensional (3D) memory devices with 3D phase-change memory (PCM) and methods for forming and operating the 3D memory devices are disclosed. In an example, a 3D memory device includes a first semiconductor structure including an array of NAND memory cells, and a first bonding layer including first bonding contacts. The 3D memory device also further includes a second semiconductor structure including a second bonding layer including second bonding contacts, a semiconductor layer and a peripheral circuit and an array of PCM cells between the second bonding layer and the semiconductor layer. The 3D memory device further includes a bonding interface between the first and second bonding layers. The first bonding contacts are in contact with the second bonding contacts at the bonding interface.

Abstract: According to one embodiment, a semiconductor storage device includes a first memory cell, a second memory cell, a first transistor, a second transistor, and a third transistor. The first transistor includes a first portion electrically connected to a first circuit, a second portion electrically connected to the first memory cell, and a first gate electrode installed between the first portion and the second portion. The second transistor includes a third portion electrically connected to the first circuit, a fourth portion electrically connected to the second memory cell, and a first gate electrode installed between the third portion and the fourth portion. The third transistor includes the second portion, the fourth portion, a fifth portion electrically connected to a second circuit, and a second gate electrode installed between the second portion and the fifth portion and between the fourth portion and the fifth portion.

Abstract: A resistive memory device includes a first word line extending in a first horizontal direction, a second word line extending on the first word line in the first horizontal direction, a third word line extending on the second word line in the first horizontal direction, a first bit line extending between the first and second word lines in a second horizontal direction, a second bit line extending between the second and third word lines in the second horizontal direction, and memory cells respectively arranged between the first word line and the first bit line, between the first bit line and the second word line, between the second word line and the second bit line, and between the second bit line and the third word line. A thickness of the second word line is greater than a thickness of each of the first word line and the third word line.

Abstract: A memory is provided which comprises a capacitor including non-linear polar material. The capacitor may have a first terminal coupled to a node (e.g., a storage node) and a second terminal coupled to a plate-line. The capacitors can be a planar capacitor or non-planar capacitor (also known as pillar capacitor). The memory includes a transistor coupled to the node and a bit-line, wherein the transistor is controllable by a word-line, wherein the plate-line is parallel to the bit-line. The memory includes a refresh circuitry to refresh charge on the capacitor periodically or at a predetermined time. The refresh circuit can utilize one or more of the endurance mechanisms. When the plate-line is parallel to the bit-line, a specific read and write scheme may be used to reduce the disturb voltage for unselected bit-cells. A different scheme is used when the plate-line is parallel to the word-line.

Abstract: The disclosure relates to systems and methods for evaluating a blood vessel. The method includes receiving image data of the blood vessel acquired by an image acquisition device, and predicting, by a processor, blood vessel condition parameters of the blood vessel by applying a deep learning model to the acquired image data of the blood vessel. The deep learning model maps a sequence of image patches on the blood vessel to blood vessel condition parameters on the blood vessel, where in the mapping the entire sequence of image patches contribute to the blood vessel condition parameters. The method further includes providing the blood vessel condition parameters of the blood vessel for evaluating the blood vessel.

Abstract: The present disclosure is directed to a circuit layout of a dual port static random-access-memory (SRAM) cell. The memory cell includes active regions in a substrate, with polysilicon gate electrodes on the active regions to define transistors of the memory cell. The eight transistor (8T) memory cell layout includes a reduced aspect ratio and non-polysilicon bit line discharge path routing by positioning an active region for the first port opposite an active region for the second port and consolidating power line nodes at a central portion of the memory cell.

Abstract: A memory is provided which comprises a capacitor including non-linear polar material. The capacitor may have a first terminal coupled to a node (e.g., a storage node) and a second terminal coupled to a plate-line. The capacitors can be a planar capacitor or non-planar capacitor (also known as pillar capacitor). The memory includes a transistor coupled to the node and a bit-line, wherein the transistor is controllable by a word-line, wherein the plate-line is parallel to the bit-line. The memory includes a refresh circuitry to refresh charge on the capacitor periodically or at a predetermined time. The refresh circuit can utilize one or more of the endurance mechanisms. When the plate-line is parallel to the bit-line, a specific read and write scheme may be used to reduce the disturb voltage for unselected bit-cells. A different scheme is used when the plate-line is parallel to the word-line.

Abstract: A ferroelectric field-effect transistor (FeFET) configured as a multi-bit storage device, the FeFET including: a semiconductor substrate that has a source region in the semiconductor substrate, and a drain region in the semiconductor substrate; a gate stack over the semiconductor substrate, with the source region and the drain region extending to opposite sides of the gate stack, the gate stack including a ferroelectric layer over the semiconductor substrate, and a gate region over the ferroelectric layer. The transistor also includes first and second ends of the ferroelectric layer which are proximal correspondingly to the source and drain regions. The ferroelectric layer includes dipoles. A first set of dipoles at the first end of the ferroelectric layer has a first polarization. A second set of dipoles at the second end of the ferroelectric layer has a second polarization, the second polarization being substantially opposite of the first polarization.