Abstract: An electrical device including a substrate structure including a relaxed region of alternating layers of at least a first semiconductor material and a second semiconductor material. A first region of the substrate structure includes a first type conductivity semiconductor device having a first strain over a first portion of the relaxed region. A second region of the substrate structure includes a second type conductivity semiconductor device having a second strain over a second portion of the relaxed region. A third region of the substrate structure including a trench capacitor extending into relaxed region, wherein a width of the trench capacitor defined by the end to end distance of the node dielectric for the trench capacitor alternates between at least two width dimensions as a function of depth measured from the upper surface of the substrate structure.

Abstract: A tunable breakdown voltage RF MESFET and/or MOSFET and methods of manufacture are disclosed. The method includes forming a first line and a second line on an underlying gate dielectric material. The second line has a width tuned to a breakdown voltage. The method further includes forming sidewall spacers on sidewalls of the first and second line such that the space between first and second line is pinched-off by the dielectric spacers. The method further includes forming source and drain regions adjacent outer edges of the first line and the second line, and removing at least the second line to form an opening between the sidewall spacers of the second line and to expose the underlying gate dielectric material. The method further includes depositing a layer of material on the underlying gate dielectric material within the opening, and forming contacts to a gate structure and the source and drain regions.

Abstract: A ferroelectric memory device may include a semiconductor substrate, a plurality of ferroelectric layers, a source, a drain and a gate. The semiconductor substrate may have a recess. The ferroelectric layers may be formed in the recess. The source may be arranged at a first side of the recess. The drain may be arranged at a second side of the recess opposite to the first side. The gate may be arranged on the ferroelectric layers. The ferroelectric layers may be polarized by different electric fields.

Abstract: A semiconductor package includes a semiconductor chip disposed on a first substrate, a mold layer covering a sidewall of the semiconductor chip and including a through-hole, a second substrate disposed on the semiconductor chip, a connection terminal disposed between the first substrate and the second substrate and provided in the through-hole, and an underfill resin layer extending from between the semiconductor chip and the second substrate into the through-hole.

Abstract: A transistor is fabricated by growing an epitaxial layer of semiconductor material on a semiconductor layer and forming an opening extending through the epitaxial layer at the gate location. This opening provides, from the epitaxial layer, a source epitaxial region on one side of the opening and a drain epitaxial region on an opposite side of the opening. The source epitaxial region and a first portion of the semiconductor layer underlying the source epitaxial region are annealed into a single crystal transistor source region. Additionally, the drain epitaxial region and a second portion of the semiconductor layer underlying the drain epitaxial region are annealed into a single crystal transistor drain region. A third portion of the semiconductor layer between the transistor source and drain regions forms a transistor channel region. A transistor gate electrode is then formed in the opening above the transistor channel region.

Abstract: The present disclosure relates to a micro-electro mechanical system (MEMS) package and a method of achieving differential pressure adjustment in multiple MEMS cavities at a wafer-to-wafer bonding level. A device substrate comprising first and second MEMS devices is bonded to a capping substrate comprising first and second recessed regions. A ventilation trench is laterally spaced apart from the recessed regions and within the second cavity. A sealing structure is arranged within the ventilation trench and defines a vent in fluid communication with the second cavity. A cap is arranged within the vent to seal the second cavity at a second gas pressure that is different than a first gas pressure of the first cavity.

Abstract: An optoelectronic semiconductor component is disclosed, comprising: a semiconductor body (1) having a semiconductor layer sequence (2) with a p-type semiconductor region (3), an n-type semiconductor region (5), and an active layer (4) arranged between the p-type semiconductor region (3) and the n-type semiconductor region (5); a support (10) having a plastic material and a first via (11) and a second via (12); a p-contact layer (7) and an n-contact layer (8), at least some regions of which are arranged between the support (10) and the semiconductor body (1), wherein the p-contact layer (7) connects the first via (11) to the p-type semiconductor region (3) and the n-contact layer (8, 8A) connects the second via (12) to the n-type semiconductor region (5); and an ESD protection element (15) which is arranged between the support (10) and the semiconductor body (1), wherein the ESD protection element (15) is electrically conductively connected to the first via (11) and to the second via (12), and wherein a forwar

Abstract: Provided is a power semiconductor device which is able to have improved connection reliability between a wiring line and an electrode of a power semiconductor element in comparison to conventional power semiconductor devices. This power semiconductor device is provided with: a semiconductor element; an insulating substrate having an electrode layer to which the semiconductor element is bonded; an external wiring line which is solder bonded to an upper surface electrode of the semiconductor element and has an end portion for external connection, said end portion being bent toward the upper surface; and a frame member which is affixed to the electrode layer of the insulating substrate. The frame member has a fitting portion that is fitted with the end portion for external connection; and the external wiring line has at least two projected portions that protrude toward the semiconductor element.

Abstract: The present disclosure includes textured memory cell structures and method of forming the same. In one or more embodiments, a memory cell includes a buffer portion formed on an amorphous portion and an active portion formed on the buffer portion, wherein the active portion is textured with a single out of plane orientation.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a fin structure formed over the substrate. The semiconductor structure further includes an isolation structure formed around the fin structure and a gate structure formed across the fin structure. In addition, the gate structure includes a first portion formed over the fin structure and a second portion formed over the isolation structure, and the second portion of the gate structure includes an extending portion extending into the isolation structure.

Abstract: To provide enhanced data storage devices and systems, various systems, architectures, apparatuses, and methods, are provided herein. In a first example, a resistive memory device is provided. The resistive memory device comprises a substrate, and an active region having resistance properties that can be modified to store one or more data bits, the active region comprising region of the substrate with a chemically altered reduction level to establish a resistive memory property in the substrate. The resistive memory device comprises terminals formed into the substrate and configured to couple the active region to associated electrical contacts.

Abstract: A method for producing an integrated power transistor circuit includes forming at least one transistor cell in a cell array, each transistor cell having a doped region formed in a semiconductor substrate and adjoining a first surface of the semiconductor substrate on a first side of the semiconductor substrate, depositing a contact layer on the first side, structuring the contact layer to form a contact structure from the contact layer, the contact structure having, in a projection of the cell array orthogonal to the first surface, a first section and, outside the cell array, a second section which connects the first section to an interface structure, and forming an electrode structure on and in direct contact with the first section in the orthogonal projection of the cell array, the electrode structure being absent outside the cell array.

Abstract: Semiconductor device structures and methods for forming the same are provided. The method for forming a semiconductor device structure includes forming a dummy gate structure over a substrate and forming a dielectric layer over the substrate around the dummy gate structure. The method for forming a semiconductor device structure further includes removing the dummy gate structure and removing a portion of the dielectric layer to form a funnel shaped trench. The method for forming a semiconductor device structure further includes forming a gate structure in a bottom portion of the funnel shaped trench and filling a hard mask material in a top portion of the funnel shaped trench to form a funnel shaped hard mask structure.

Abstract: Provided are methods for verifying sequences of different operations and controlling processing order in accordance with these sequences. Also provided are apparatuses for executing these methods. A method may involve determining a current configuration of an indicator positioned on a part. This operation may be performed using a tester coupled to a processing portion. If the current configuration of the indicator corresponds to this particular processing portion, then the part is processed using this processing portion. The indicator is then changed to a new configuration corresponding to another processing portion for performing the next operation in the sequence. The processing is only performed if the indicator has the current configuration corresponding to the processing portion. Otherwise, the operation is not performed, and the current configuration of the indicator not changed retained. The indicator may be a mechanical device or an electronic device.

Abstract: A vertical, single column compound semiconductor bipolar junction transistor device includes an all-around extrinsic base. Homojunction and heterojunction devices are formed using III-V compound semiconductor materials with appropriate bandgaps. Fabrication of the transistor device includes epitaxially growing a III-V compound semiconductor base region on a heavily doped III-V compound semiconductor bottom layer. A polycrystalline emitter/collector layer and the all-around extrinsic base are grown on the base region.

Abstract: An electrical device including a substrate structure including a relaxed region of alternating layers of at least a first semiconductor material and a second semiconductor material. A first region of the substrate structure includes a first type conductivity semiconductor device having a first strain over a first portion of the relaxed region. A second region of the substrate structure includes a second type conductivity semiconductor device having a second strain over a second portion of the relaxed region. A third region of the substrate structure including a trench capacitor extending into relaxed region, wherein a width of the trench capacitor defined by the end to end distance of the node dielectric for the trench capacitor alternates between at least two width dimensions as a function of depth measured from the upper surface of the substrate structure.

Abstract: A sensor comprises a substrate 16 and a sensor element 20 anchored to the substrate 16, the substrate 16 and sensor element 20 being of dissimilar materials and having different coefficients of thermal expansion, the sensor element 20 and substrate 16 each having a generally planar face arranged substantially parallel to one another, the sensor further comprising a spacer 26, the spacer 26 being located so as to space at least part of the sensor element 20 from at least part of the substrate 16, wherein the spacer 26 is of considerably smaller area than the area of the smaller of face of the substrate 16 and that of the sensor element 20.

Abstract: A semiconductor structure, device, or vertical field effect transistor is comprised of a drain, a drift layer disposed in a first direction relative to the drain and in electronic communication with the drain, a barrier layer disposed in the first direction relative to the drift layer and in electronic communication with the drain, the barrier layer comprising a current blocking layer and an aperture region, a two-dimensional hole gas-containing layer disposed in the first direction relative to the barrier layer, a gate electrode oriented to alter an energy level of the aperture region when a gate voltage is applied to the gate electrode, and a source in ohmic contact with the two-dimensional hole gas-containing layer. At least one of an additional layer, the drain, the drift region, the current blocking layer, the two-dimensional hole gas-containing layer, and the aperture region comprises diamond.

Abstract: There is provided a light emitting element package including: a light emitting laminate having a structure in which semiconductor layers are laminated and having a first main surface and a second main surface opposing the first main surface; a terminal unit disposed on an electrode disposed on the second main surface; a molded unit disposed on the second main surface of the light emitting laminate and allowing a portion of the terminal unit to be exposed; and a wavelength conversion unit disposed on the first main surface of the light emitting laminate.

Abstract: In accordance with an embodiment of the present invention, a method of forming a densified fill layer is provided. The method includes forming a pair of adjacent vertical fins on a substrate, forming an inner liner on the sidewalls of the adjacent vertical fins, and forming a sacrificial layer on the inner liner. The method further includes forming a fill layer between the pair of adjacent vertical fins, wherein the fill layer is in contact with at least a portion of the sacrificial layer, removing at least a portion of the sacrificial layer in contact with the fill layer to form sidewall channels adjacent to the fill layer, and subjecting the fill layer to a densification process to form the densified fill layer.