Abstract: An embedded flash memory device includes a gate stack, which includes a bottom dielectric layer extending into a recess in a semiconductor substrate, and a charge storage layer over the bottom dielectric layer. The charge storage layer includes a portion in the recess. The gate stack further includes a top dielectric layer over the charge storage layer, and a metal gate over the top dielectric layer. Source and drain regions are in the semiconductor substrate, and are on opposite sides of the gate stack.

Abstract: A method includes forming a gate stack over a semiconductor region, depositing an impurity layer over the semiconductor region, and depositing a metal layer over the impurity layer. An annealing is then performed, wherein the elements in the impurity layer are diffused into a portion of the semiconductor region by the annealing to form a source/drain region, and wherein the metal layer reacts with a surface layer of the portion of the semiconductor region to form a source/drain silicide region over the source/drain region.

Abstract: A method for forming a semiconductor device comprises forming a gate stack on a channel region of a semiconductor, forming a source/drain region adjacent to the channel region, depositing a first insulator layer over the source/drain region, and removing a portion of the first insulator layer to form a first cavity that exposes a portion of the source/drain region. A first conductive material is deposited in the first cavity, and a conductive extension is formed from the first conductive material over the first insulator layer. A protective layer is deposited over the extension and a second insulator layer is deposited over the protective layer. A portion of the second insulator layer is removed to form a second cavity that exposes the protective layer, and an exposed portion of the protective layer is removed to expose a portion of the extension. A second conductive material is deposited in the second cavity.

Abstract: A fabrication method includes preparing a base substrate, the base substrate including a pixel region and a region of gate on array (GOA); forming a pattern including a gate electrode and a pattern of an active layer on the base substrate, and forming a gate lead on the region of GOA, by a first patterning process; forming a pattern of a gate insulating layer by a second patterning process; forming a pattern including a source/drain electrode by a third patterning process; forming a pattern of a planarization layer by a fourth patterning layer; and forming a pattern including a pixel electrode by a fifth patterning layer. Here, the pattern including the gate electrode and the pattern including the active layer are formed by one patterning process, which can reduce the number of masks in the fabrication process of the array substrate, improve production efficiency and save the cost.

Abstract: A semiconductor device includes a semiconductor pattern on a substrate along a first direction, a blocking pattern on a top surface of the semiconductor pattern, a first wire pattern on the blocking pattern along a second direction different from the first direction, the first wire including a first part and a second part on opposite sides of the first part, a gate electrode surrounding the first part of the first wire pattern, and a contact surrounding the second part of the first wire pattern, wherein a height of a bottom surface of the contact from a top surface of the substrate is different from a height of a bottom surface of the gate electrode from the top surface of the substrate.

Abstract: An optoelectronic semiconductor chip includes a carrier and a semiconductor body having an active layer that generates electromagnetic radiation, wherein the semiconductor body is arranged on the carrier, the semiconductor body has a first main surface facing away from the carrier and a second main surface facing the carrier, the semiconductor chip has a side surface having an anchoring structure, and the second main surface is arranged between the first main surface and the anchoring structure.

Abstract: A switching device includes a first electrode and a second electrode, and an electrolyte layer disposed between the first electrode and the second electrode. The electrolyte layer includes a first layer charged with negative charges and a second layer charged with positive charges.

Abstract: A tunable breakdown voltage RF MESFET and/or MOSFET and methods of manufacture are disclosed. The method includes forming a first line and a second line on an underlying gate dielectric material. The second line has a width tuned to a breakdown voltage. The method further includes forming sidewall spacers on sidewalls of the first and second line such that the space between first and second line is pinched-off by the dielectric spacers. The method further includes forming source and drain regions adjacent outer edges of the first line and the second line, and removing at least the second line to form an opening between the sidewall spacers of the second line and to expose the underlying gate dielectric material. The method further includes depositing a layer of material on the underlying gate dielectric material within the opening, and forming contacts to a gate structure and the source and drain regions.

Abstract: An electrical device including a substrate structure including a relaxed region of alternating layers of at least a first semiconductor material and a second semiconductor material. A first region of the substrate structure includes a first type conductivity semiconductor device having a first strain over a first portion of the relaxed region. A second region of the substrate structure includes a second type conductivity semiconductor device having a second strain over a second portion of the relaxed region. A third region of the substrate structure including a trench capacitor extending into relaxed region, wherein a width of the trench capacitor defined by the end to end distance of the node dielectric for the trench capacitor alternates between at least two width dimensions as a function of depth measured from the upper surface of the substrate structure.

Abstract: A tunable breakdown voltage RF MESFET and/or MOSFET and methods of manufacture are disclosed. The method includes forming a first line and a second line on an underlying gate dielectric material. The second line has a width tuned to a breakdown voltage. The method further includes forming sidewall spacers on sidewalls of the first and second line such that the space between first and second line is pinched-off by the dielectric spacers. The method further includes forming source and drain regions adjacent outer edges of the first line and the second line, and removing at least the second line to form an opening between the sidewall spacers of the second line and to expose the underlying gate dielectric material. The method further includes depositing a layer of material on the underlying gate dielectric material within the opening, and forming contacts to a gate structure and the source and drain regions.

Abstract: A semiconductor device with favorable electrical characteristics is provided. Alternatively, a semiconductor device with a high on-state current is provided. Alternatively, a semiconductor device that is suitable for miniaturization is provided. A semiconductor device includes an oxide semiconductor, an insulating film, a gate insulating film, and a gate electrode. The oxide semiconductor includes a first portion and a second portion over the first portion. The insulating film includes a region in contact with a side surface of the first portion. The gate electrode includes a region that covers the second portion with the gate insulating film provided therebetween.

Abstract: In one aspect, a method of forming a local interconnect structure includes the steps of: forming a BOX SOI wafer having a fully depleted seed layer between a first BOX layer and a second BOX layer, and an active layer over the second BOX layer; forming at least one STI region in the active layer having an STI oxide; forming at least one trench that extends through the STI oxide and the second BOX layer down to the seed layer, wherein the trench has a footprint and a location such that a portion of the STI oxide remains lining sidewalls of the trench; and growing an epitaxial material in the trench using the seed layer as a template for the growth, wherein the epitaxial material is doped and serves as the local interconnect structure which is buried in the double BOX SOI wafer.

Abstract: A thin film transistor (TFT), a method for fabricating the same, an array substrate and a display device are provided. The TFT includes a source electrode and a drain electrode, a semiconductor active layer, a gate insulating layer and a gate electrode. The TFT further includes a light-shielding layer between the source electrode and the drain electrode. The light-shielding layer separates the source electrode and the drain electrode, and the light-shielding layer is disposed on a light incident side of the semiconductor active layer and is used to prevent the incident light from irradiating on the semiconductor active layer.

Abstract: One illustrative method disclosed includes, among other things, forming an initial conductive source/drain structure that is conductively coupled to a source/drain region of a transistor device, performing a recess etching process on the initial conductive source/drain structure to thereby define a stepped conductive source/drain structure with a cavity defined therein, forming a non-conductive structure in the cavity, forming a layer of insulating material above the gate structure, the stepped conductive source/drain structure and the non-conductive structure, forming a gate contact opening in the layer of insulating material and forming a conductive gate contact in the gate contact opening that is conductively coupled to the gate structure.

Abstract: A tunable breakdown voltage RF MESFET and/or MOSFET and methods of manufacture are disclosed. The method includes forming a first line and a second line on an underlying gate dielectric material. The second line has a width tuned to a breakdown voltage. The method further includes forming sidewall spacers on sidewalls of the first and second line such that the space between first and second line is pinched-off by the dielectric spacers. The method further includes forming source and drain regions adjacent outer edges of the first line and the second line, and removing at least the second line to form an opening between the sidewall spacers of the second line and to expose the underlying gate dielectric material. The method further includes depositing a layer of material on the underlying gate dielectric material within the opening, and forming contacts to a gate structure and the source and drain regions.

Abstract: An OLED packaging method includes providing a substrate on which an OLED device is formed and a package lid that comprises a trough formed to correspond to the OLED device and receive a solid resin film therein, forming a loop of fritted glass on the package lid and outside the trough, forming a loop of inorganic protective frame made of silicon nitride on the substrate and at a location that is outside the trough and inside the fritted glass, forming a loop of adhesive on the package lid to correspond to the inorganic protective frame, and laminating the package lid and the substrate to each other such that the OLED device is covered by the solid resin film and the inorganic protective frame is adhered to the adhesive to form a combined circumferential wall, which surrounds, together with the fritted glass, the OLED device covered by the solid resin film.

Abstract: In an embodiment, an electronic component includes a dielectric core layer having a thickness, at least one semiconductor die embedded in the dielectric core layer and electrically coupled to at least one contact pad arranged on a first side of the dielectric core layer, and a heat dissipation layer arranged on a second side of the dielectric core layer and thermally coupled to the semiconductor die. The semiconductor die has a thickness that is substantially equal to, or greater than, or equal to the thickness of the dielectric core layer. The heat dissipation layer includes a material with a substantially isotropic thermal conductivity.

Abstract: A method of manufacturing a semiconductor device includes preparing a layer, including columns, the columns extend a first direction parallel to the surface of the layer, the columns are arranged at intervals, interdigitally sandwiching other columns so as to implement a superjunction structure so the columns and the other columns are side by side; forming well regions in the layer; forming source regions in the well regions; forming an insulating film on the well regions; and forming gate electrodes on the gate insulating film, the gate electrodes bridging corresponding source regions in neighboring well regions, a temperature detection diode at an area in the gate electrodes, one column has a first width in a second direction, the temperature detection diode has a second width in the second direction, and the first width equal to the second width, and the second direction is perpendicular to the first direction.

Abstract: To provide enhanced data storage devices and systems, various systems, architectures, apparatuses, and methods, are provided herein. In a first example, a resistive memory device is provided. The resistive memory device comprises a substrate, and an active region having resistance properties that can be modified to store one or more data bits, the active region comprising region of the substrate with a chemically altered reduction level to establish a resistive memory property in the substrate. The resistive memory device comprises terminals formed into the substrate and configured to couple the active region to associated electrical contacts.

Abstract: The present invention provides a laterally diffused metal-oxide-semiconductor (LDMOS) transistor and a manufacturing method thereof. The LDMOS transistor includes a semiconductor substrate, an insulation structure, agate structure, and a plurality of floating electrodes. The insulation structure is disposed in the semiconductor substrate. The gate structure is disposed on the semiconductor substrate. The floating electrodes are embedded in the insulation structure, wherein the floating electrode closest to the gate structure protrudes from a top surface of the insulation structure or the gate structure includes at least one branch portion embedded in the insulation structure, and the floating electrodes are separated from the gate structure.