Abstract: A memory cell includes a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element. The memory cell is formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor. The gate is formed on the active layer and has a lateral flank covered with a second insulating layer. The variable-resistance element includes a first layer covering a lateral flank of the active layer in a trench formed through the active layer along the lateral flank of the gate and reaching the first insulating layer, and a second layer made of a variable-resistance material.

Abstract: Generally, the present disclosure provides example embodiments relating to formation of a gate structure of a device, such as in a replacement gate process, and the device formed thereby. In an example method, a gate dielectric layer is formed over an active area on a substrate. A dummy layer that contains a passivating species (such as fluorine) is formed over the gate dielectric layer. A thermal process is performed to drive the passivating species from the dummy layer into the gate dielectric layer. The dummy layer is removed. A metal gate electrode is formed over the gate dielectric layer. The gate dielectric layer includes the passivating species before the metal gate electrode is formed.

Abstract: The present disclosure relates to a large scale film containing quantum dots or a dye, a method of preparing the large scale film, including: forming quantum dots or a dye dispersed in a solvent in the form of fibers or beads; applying pressure to an adhesive film to make the fibers or the beads adhere thereto; and curing the adhesive film onto which the fibers or the beads have adhered, and fibers or beads of quantum dots or a dye which are prepared by electrospinning.

Abstract: A power module will be provided which can suppress insulation performance deterioration caused by heat cycle to ensure insulation performance, by suppressing generation of bubbles and occurrence of detachments between silicone gel and an insulating substrate at a high or low temperature or at a high working voltage.

Abstract: A display device is disclosed. In one aspect, the display device includes a display area configured to display an image, a peripheral area neighboring the display area, and at least one test element group (TEG) including a test thin film transistor (TFT) formed in the peripheral area and a plurality of test pads electrically connected to the test TFT. The display device also includes first to third dummy circuits separated from the test TFT, each of the first to third dummy circuits including a plurality of first dummy semiconductor layers and a plurality of first dummy gate electrodes overlapping at least a portion of the first dummy semiconductor layers in the depth dimension of the display device.

Abstract: Provided is a vehicle-mounted semiconductor device enabling a temperature increase of active elements to be restricted. A vehicle-mounted semiconductor device includes: a semiconductor substrate; a plurality of active elements formed on the semiconductor substrate; a plurality of trenches surrounding the plurality of active elements to insulate and separate the active elements; and a terminal connecting in parallel the plurality of active elements insulated and separated by different trenches among the plurality of trenches and connected to an outside.

Abstract: The present specification discloses a semiconductor device and a method for manufacturing same.

Abstract: A vehicle power module for converting power includes a lead frame configured to receive power from outside or to output power to the outside and a substrate configured to be bonded with the lead frame. The substrate includes a pattern layer disposed to be electrically connected to the lead frame, a conductive layer disposed apart from the pattern layer and configured to be electrically grounded, and an insulating layer disposed between the conductive layer and the pattern layer to insulate the pattern layer from the conductive layer. The pattern layer further protrudes toward the lead frame than the insulating layer.

Abstract: A light-emitting device includes an emission structure, a current block layer on the emission structure, a reflective layer on the current block layer, a protection layer that covers the reflective layer, and an electrode layer on the protection layer.

Abstract: A chip-on film and a display device including the same are disclosed. The chip-on film includes a first base film, a second base film positioned on the first base film, a film pad portion positioned on at least one side of the second base film and exposed to the outside of the first base film, and a coating layer positioned on one surface of the first base film.

Abstract: A semiconductor chip has a first transistor that amplifies a first signal and outputs a second signal, a second transistor that amplifies the second signal and outputs a third signal, and a semiconductor substrate having a main surface parallel to a plane defined by first and second directions and which has the first and second transistors formed thereon. The main surface has thereon a first bump connected to a collector or drain of the first transistor, a second bump connected to an emitter or source of the first transistor, a third bump connected to a collector or drain of the second transistor, and a fourth bump connected to an emitter or source of the second transistor. The first bump is circular, the second through fourth bumps are rectangular or oval, and the area of each of the second through fourth bumps is larger than that of the first bump.

Abstract: The present disclosure relates to a micro-electro mechanical system (MEMS) package and a method of achieving differential pressure adjustment in multiple MEMS cavities at a wafer-to-wafer bonding level. In some embodiments, a ventilation trench and an isolation trench are concurrently within a capping substrate. The isolation trench isolates a silicon region and has a height substantially equal to a height of the ventilation trench. A sealing structure is formed within the ventilation trench and the isolation trench, the sealing structure filing the isolation trench and defining a vent within the ventilation trench. A device substrate is provided and bonded to the capping substrate at a first gas pressure and hermetically sealing a first cavity associated with a first MEMS device and a second cavity associated with a second MEMS device. The capping substrate is thinned to open the vent to adjust a gas pressure of the second cavity.

Abstract: To provide a nitride semiconductor element having a better contact resistance reduction effect also in the case of a light emitting element containing AlGaN having a high Al composition. The nitride semiconductor element has a substrate 1, a first conductivity type first nitride semiconductor layer 2 formed on the substrate 1, and a first electrode layer 4 formed on the first nitride semiconductor layer 2. The first electrode layer 4 contains aluminum and nickel, and both aluminum and an alloy containing aluminum and nickel are present in a contact surface to the first nitride semiconductor layer 2 or in the vicinity of the contact surface.

Abstract: A light-emitting device includes an emission structure, a current block layer on the emission structure, a reflective layer on the current block layer, a protection layer that covers the reflective layer, and an electrode layer on the protection layer.

Abstract: Provided is a semiconductor device including an interconnection structure provided on a cell region of a substrate to include a first line and a second line sequentially stacked on the substrate, and a defect detection structure provided on a peripheral region of the substrate to include first and second defect detection lines provided at the same levels as those of the first and second lines, respectively.

Abstract: A semiconductor device includes a semiconductor substrate in which an active region and an edge termination region are defined, a semiconductor element formed in the active region, and first to fourth P layers formed in a region spanning from an edge portion of the active region to the edge termination region in the surface of the semiconductor substrate. The first to fourth P layers respectively have surface concentrations P(1) to P(4) that decrease in this order, bottom-end distances D(1) to D(4) that increase in this order, and distances B(1) to B(4) to the edge of the semiconductor substrate that increase in this order. The surface concentration P(4) is 10 to 1000 times the impurity concentration of the semiconductor substrate, and the bottom-end distance D(4) is in the range of 15 to 30 ?m.

Abstract: The present disclosure relates to a micro-electro mechanical system (MEMS) package and a method of achieving differential pressure adjustment in multiple MEMS cavities at a wafer-to-wafer bonding level. A device substrate comprising first and second MEMS devices is bonded to a capping substrate comprising first and second recessed regions. A ventilation trench is laterally spaced apart from the recessed regions and within the second cavity. A sealing structure is arranged within the ventilation trench and defines a vent in fluid communication with the second cavity. A cap is arranged within the vent to seal the second cavity at a second gas pressure that is different than a first gas pressure of the first cavity.

Abstract: A transistor is fabricated by growing an epitaxial layer of semiconductor material on a semiconductor layer and forming an opening extending through the epitaxial layer at the gate location. This opening provides, from the epitaxial layer, a source epitaxial region on one side of the opening and a drain epitaxial region on an opposite side of the opening. The source epitaxial region and a first portion of the semiconductor layer underlying the source epitaxial region are annealed into a single crystal transistor source region. Additionally, the drain epitaxial region and a second portion of the semiconductor layer underlying the drain epitaxial region are annealed into a single crystal transistor drain region. A third portion of the semiconductor layer between the transistor source and drain regions forms a transistor channel region. A transistor gate electrode is then formed in the opening above the transistor channel region.

Abstract: A transistor excellent in electrical characteristics and a method for manufacturing the transistor are provided. The transistor includes an oxide semiconductor layer including a source region, a drain region, and a channel formation region over an insulating surface; a gate insulating film over the oxide semiconductor layer; a gate electrode overlapping with the channel formation region, over the gate insulating film; a source electrode in contact with the source region; and a drain electrode in contact with the drain region. The source region and the drain region include a portion having higher oxygen concentration than the channel formation region.

Abstract: A wrap-around source/drain trench contact structure is described. A plurality of semiconductor fins extend from a semiconductor substrate. A channel region is disposed in each fin between a pair of source/drain regions. An epitaxial semiconductor layer covers the top surface and sidewall surfaces of each fin over the source/drain regions, defining high aspect ratio gaps between adjacent fins. A pair of source/drain trench contacts are electrically coupled to the epitaxial semiconductor layers. The source/drain trench contacts comprise a conformal metal layer and a fill metal. The conformal metal layer conforms to the epitaxial semiconductor layers. The fill metal comprises a plug and a barrier layer, wherein the plug fills a contact trench formed above the fins and the conformal metal layer, and the barrier layer lines the plug to prevent interdiffusion of the conformal metal layer material and plug material.