Patents Examined by Vinh P. Nguyen
  • Patent number: 11609264
    Abstract: There is provided an attenuation amount setting unit that sets, in a case where signals are simultaneously output from all output ports of a plurality of interface units at the same signal level, one of the plurality of interface units as the reference interface unit, and adds a difference between an attenuation amount of a second attenuator stored in a storage unit of the reference interface unit and an attenuation amount of another second attenuator stored in another storage unit of the other interface unit to an attenuation amount of each of a plurality of third attenuators of the other interface unit to correct the attenuation amount.
    Type: Grant
    Filed: December 7, 2021
    Date of Patent: March 21, 2023
    Assignee: ANRITSU CORPORATION
    Inventors: Koichiro Tomisaki, Jesse Paulo Valencia Macabasco
  • Patent number: 11609203
    Abstract: The disclosure describes techniques for detecting a crack or defect in a material. The technique may include applying an electrical signal to a first electrode pair electrically coupled to the material. The technique also may include, while applying the electrical signal to the first electrode pair, determining a measured voltage between a second, different electrode pair. At least one electrode of the second, different electrode pair is electrically coupled to the material. The technique may further include determining a corrected measured voltage by suppressing a thermally induced voltage from the measured voltage and determining whether the material includes a crack or other defect based on the corrected measured voltage.
    Type: Grant
    Filed: June 9, 2021
    Date of Patent: March 21, 2023
    Assignee: 3M Innovative Properties Company
    Inventors: David H. Redinger, Christopher R. Yungers, Jennifer F. Schumacher
  • Patent number: 11609262
    Abstract: An integrated circuit die includes a core fabric configurable to include an aging measurement circuit and a device manager coupled to the core fabric to operate the aging measurement circuit for a select period of time. The aging measurement circuit includes a counter to count transitions of a signal propagating through the aging measurement circuit during the select period of time when the aging measurement circuit is operating. The transitions of the signal counted by the counter during the select period of time are a measure of an aging characteristic of the integrated circuit die.
    Type: Grant
    Filed: December 25, 2018
    Date of Patent: March 21, 2023
    Assignee: Intel Corporation
    Inventors: Dheeraj Subbareddy, Ankireddy Nalamalpu, Mahesh A. Iyer, Dhananjay Raghavan
  • Patent number: 11598820
    Abstract: A load testing device includes: a resistance unit; a cooling fan that cools the resistance unit; a circuit breaker; a first terminal part that is connected to a test target power source; and a charge/discharge unit that has a charger and a first power storage device. The charge/discharge unit is connected with a test target power source cable being between the first terminal part and the resistance unit, between the first terminal part and the circuit breaker. The first power storage device 45a stores electric power supplied from the test target power source. The cooling fan drives based on electric power from at least the charge/discharge unit.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: March 7, 2023
    Assignee: TATSUMI RYOKI CO., LTD
    Inventor: Toyoshi Kondo
  • Patent number: 11600539
    Abstract: A semiconductor device includes a semiconductor die, a defect detection structure and an input-output circuit. The semiconductor die includes a central region and a peripheral region surrounding the central region. The peripheral region includes a left-bottom corner region, a left-upper corner region, a right-upper corner region and a right-bottom corner region. The defect detection structure is formed in the peripheral region. The defect detection structure includes a first conduction loop in the left-bottom corner region, a second conduction loop in the right-bottom corner region, a third conduction loop in the left-bottom corner region and the left-upper corner region and a fourth conduction loop in the right-bottom corner region and the right-upper corner region. The input-output circuit is electrically connected to end nodes of the first conduction loop, the second conduction loop, the third conduction loop and the fourth conduction loop.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: March 7, 2023
    Inventors: Min-Jae Lee, Sang-Lok Kim, Byung-Hoon Jeong, Tae-Sung Lee, Jeong-Don Ihm, Jae-Yong Jeong, Young-Don Choi
  • Patent number: 11598815
    Abstract: This application relates to a battery test system and a battery test method. The battery test system according to an embodiment comprises: an extrusion apparatus configured to be disposed on a first surface of a battery; and a pressure apparatus, disposed above the extrusion apparatus, where the pressure apparatus is configured to apply a predetermined force to the battery in predetermined duration through the extrusion apparatus. The battery test system and the battery test method provided in this application are able to more reasonably evaluate the safety of the soft package battery and identify the risk caused by the defect of the soft package battery.
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: March 7, 2023
    Assignee: NINGDE AMPEREX TECHNOLOGY LIMITED
    Inventors: Xiaoqing Yu, Shi Tan, Zhu Feng, Zhiwen Xiao
  • Patent number: 11592472
    Abstract: An apparatus for testing integrated circuits (ICs) , includes a first thermal contact structure having a first surface to interface with a heat source and an opposing second surface to interface with a device under test (DUT). A second thermal contact structure is above the first thermal contact structure and separated therefrom by a variable-resistance thermal interface (VRTI) structure operable to couple or decouple the first and second thermal contact structures from one another. The VRTI structure has a maximal thermal conductivity associated with a first state, and a minimal thermal conductivity associated with a second state.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: February 28, 2023
    Assignee: Intel Corporation
    Inventors: Joe F. Walczyk, James Hastings, Morten Jensen, Todd Coons
  • Patent number: 11592497
    Abstract: A method for monitoring one or more characteristics of an ultracapacitor is provided. The method includes obtaining a plurality of voltage measurements. Each of the voltage measurements can be obtained sequentially at one of a plurality of intervals. Furthermore, each of the voltage measurements can be indicative of a voltage across the ultracapacitor. The method can include determining an actual voltage step of the ultracapacitor based on two consecutive voltage measurements of the plurality of voltage measurements. The method can further include determining whether the actual voltage step exceeds a threshold voltage step of the ultracapacitor. Furthermore, in response to determining the actual voltage step exceeds the threshold voltage, the method can include providing a notification associated with performing a maintenance action on the ultracapacitor.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: February 28, 2023
    Assignee: KYOCERA AVX COMPONENTS CORPORATION
    Inventor: Joseph M. Hock
  • Patent number: 11579171
    Abstract: Probe cards for probing highly-scaled integrated circuits are provided. A probe card includes a backplane and an array of probes extending from the backplane. Each of the probes includes a cantilever member and a probe tip. A first end of the cantilever member is coupled to the backplane, such that the cantilever member extends from the backplane. The probe tip extends from a second end of the cantilever member. The probes are fabricated from semiconductor materials. Each probe is configured to transmit electrical signals between the backplane and a device under test (DUT), via corresponding electrodes of the DUT. The probes are highly-scaled such that the feature size and pitch of the probes matches the highly-scaled feature size and pitch of the DUT's electrodes. The probes comprise atomic force microscopy (AFM) probes that are enhanced for increased electrical conductivity, elasticity, lifetime, and reliability.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: February 14, 2023
    Assignee: Meta Platforms Technologies, LLC
    Inventor: Christopher Percival
  • Patent number: 11578925
    Abstract: A thermal management system for a test-and-measurement probe that includes a thermally insulated shroud and a fluid inlet conduit. The shroud is configured to enclose a first portion of a probe head of the probe within an interior cavity of the shroud, while permitting a second portion of the probe head to extend out of the shroud. The shroud further includes a fluid outlet passageway configured to permit a heat-transfer fluid to pass from a probe-head end of the interior cavity, through the interior cavity of the shroud, and out of the shroud through an access portion of the shroud. The fluid inlet conduit enters the shroud through the access portion of the shroud, extends through the interior cavity of the shroud, and is configured to introduce the heat-transfer fluid to the probe-head end of the interior cavity.
    Type: Grant
    Filed: November 12, 2020
    Date of Patent: February 14, 2023
    Assignee: Tektronix, Inc.
    Inventors: Julie A. Campbell, David Thomas Engquist, Sam J. Strickling
  • Patent number: 11577623
    Abstract: The present invention relates to a system for predicting battery usage habits and battery discharge tendencies. The system includes a battery sensor that senses a state of charge (SOC) of a battery and a controller hat calculates battery power generation amount during driving time of a vehicle and battery consumption during parking time of the vehicle based on information sensed by the battery sensor. A storage unit for stores the battery power generation amount, the battery consumption, time at which the vehicle is tuned on/off, and time at which the controller enters a sleep/wake-up state.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: February 14, 2023
    Assignees: Hyundai Motor Company, Kia Motors Corporation, Yura Corporation Co., Ltd.
    Inventors: Hyun Wook Kim, Hyun Young Kim, Chan Young Jung
  • Patent number: 11579007
    Abstract: A method for calibrating a device for measuring a mass of fuel carried by an aircraft by: receiving a message containing a reference permittivity, a reference density and a reference volume, determining a first calibration coefficient as a function of the reference permittivity, determining a second calibration coefficient as a function of the reference volume, determining a third coefficient of calibration as a function of the reference density, determining a calibrated mass of fuel as a function of a determined height of fuel corrected as a function of the first calibration coefficient, a volume of fuel determined as a function of the corrected height and corrected as a function of the second calibration coefficient, and a mass of fuel determined as a function of the corrected volume and corrected as a function of the third calibration coefficient.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: February 14, 2023
    Assignee: Airbus Operations SAS
    Inventors: Emre Kanyilmaz, Alvaro Ruiz Gallardo
  • Patent number: 11579186
    Abstract: A burn-in board management system includes a production burn-in apparatus and a burn-in board status computer. The production burn-in apparatus is configured to test a plurality of integrated circuit devices mounted in slots of a burn-in board and comprising a first controller configured to generate a first burn-in board status map, wherein the first controller is further configured to suspend the burn-in board when the first burn-in board status map of the burn-in board demonstrates that more than a threshold percentage of the slots of the burn-in board are determined to be malfunctioned. The burn-in board status computer is communicably connected with the first controller of the production burn-in apparatus and configured to receive the first burn-in board status map.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: February 14, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Cheng-Sung Lai
  • Patent number: 11573072
    Abstract: Systems and methods are provided for determining a position of a magnet. The systems and methods utilize a first sensor located at a first sensor position and arranged to measure at least two components of a magnetic field produced by the magnet, a second sensor located at a second sensor position and arranged to measure at least two components of the magnetic field produced by the magnet, and processing circuitry operatively connected to the first and second sensors to receive signals derived from signals outputted by the first and second sensors. A field angle is calculated from a first differential field of a first field dimension and a second differential field of a second field dimension orthogonal to the first field dimension. The first and second differential fields are calculated based on signals outputted by the first and second sensors.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: February 7, 2023
    Assignee: Analog Devices International Unlimited Company
    Inventor: Jochen Schmitt
  • Patent number: 11572780
    Abstract: Impedance is used to determine the performance of paraffin inhibitors in oil containing paraffin. The method and system can use a specially designed impedance cell having a cell constant of less than 1 cm?1. Further, the method can include obtaining at least impedance measurements above the wax appearance temperature (WAT) for an oil sample treated with a paraffin inhibitor and an oil sample not treated, and impedance measurements below the WAT for the treated oil sample and the untreated oil sample. Thereafter, the impedance measurements are correlated to determine paraffin inhibitor performance.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: February 7, 2023
    Assignee: The University of Tulsa
    Inventors: Marc Tappert, Dale Teeters
  • Patent number: 11573207
    Abstract: An object perspective detector including an electric field sensing module, a signal processing module, a battery module, an analog digital conversion module, a human-machine interface analysis module and a radio transmission module. The electric field sensing module is electrically connected to the signal processing module to form a loop. The electric field sensing module which receives electric field intensity changes to generate electric signals, can be an antenna of capacitor medium, convenient for changing the detection space.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: February 7, 2023
    Inventors: Tzu-How Chu, Pi-Pai Chang
  • Patent number: 11567119
    Abstract: A stand-alone active thermal interposer device for use in testing a system-in-package device under test (DUT), the active thermal interposer device includes a body layer having a first surface and a second surface, wherein the first surface is operable to be disposed adjacent to a cold plate, and a plurality of heating zones defined across a second surface of the body layer, the plurality of heating zones operable to be controlled by a thermal controller to selectively heat and maintain respective temperatures thereof, the plurality of heating zones operable to heat a plurality of areas of the DUT when the second surface of the body layer is disposed adjacent to an interface surface of the DUT during testing of the DUT.
    Type: Grant
    Filed: November 19, 2021
    Date of Patent: January 31, 2023
    Assignee: Advantest Test Solutions, Inc.
    Inventors: Samer Kabbani, Paul Ferrari, Ikeda Hiroki, Kiyokawa Toshiyuki, Gregory Cruzan, Karthik Ranganathan, Todd Berk, Ian Williams, Mohammad Ghazvini, Thomas Jones
  • Patent number: 11566949
    Abstract: The present invention relates to a method and device for measuring the temperature in power resistors based on the measurement of the high-frequency circuit parameters of said resistor. The present invention excludes the use of thermocouples, dedicated temperature sensors or thermo chambers.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: January 31, 2023
    Assignee: I.R.C.A. S.P.A. INDUSTRIA RESISTENZE CORAZZATE E AFFINI
    Inventors: Federico Zoppas, Nicola Moret, Antonio De Moliner, Michele Peterle, Michele Midrio, Antonio Affanni
  • Patent number: 11561243
    Abstract: A wafer test device and methods of assembling a wafer test device involve a first laminate structure, and a second laminate structure arranged to interface with a microcircuit of the wafer. The wafer test device includes a compliant layer between the first laminate structure and the second laminate structure. The compliant layer includes an elastomer that exhibits compliance within a limited range of movement.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: January 24, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David Audette, Grant Wagner, Marc Knox, Dennis Conti
  • Patent number: 11555871
    Abstract: A method of detecting a biological sample includes the following steps. A magnetic sensor chip is provided, wherein the magnetic sensor chip includes a substrate and a magnetic sensing layer located on the substrate. Probes are connected to the magnetic sensor chip. A sample solution containing biological samples labeled with a first marker is provided on the magnetic sensor chip, so that the biological samples labeled with the first marker are hybridized with the probes. Magnetic beads labeled with a second marker are provided on the magnetic sensor chip, so that the magnetic beads labeled with the second marker are bound onto the biological samples labeled with the first marker. A signal sensed by the magnetic sensing layer is detected by a magnetic sensor.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: January 17, 2023
    Assignee: Industrial Technology Research Institute
    Inventors: Cheng-Tai Chen, Shih-Ya Chen, Yi-Chen Liu, Ching-Fang Lu, Chia-Chen Chang, Erh-Fang Lee