Patents Examined by Vongsavanh Sengdara
  • Patent number: 11177162
    Abstract: Techniques for forming trapezoidal-shaped interconnects are provided. In one aspect, a method for forming an interconnect structure includes: patterning a trench(es) in a dielectric having a V-shaped profile with a rounded bottom; depositing a liner into the trench(es) using PVD which opens-up the trench(es) creating a trapezoidal-shaped profile in the trench(es); removing the liner from the trench(es) selective to the dielectric whereby, following the removing, the trench(es) having the trapezoidal-shaped profile remains in the dielectric; depositing a conformal barrier layer into and lining the trench(es) having the trapezoidal-shaped profile; depositing a conductor into and filling the trench(es) having the trapezoidal-shaped profile over the conformal barrier layer; and polishing the conductor and the conformal barrier layer down to the dielectric. An interconnect structure is also provided.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: November 16, 2021
    Assignee: International Business Machines Corporation
    Inventors: Nicholas Anthony Lanzillo, Hosadurga Shobha, Huai Huang, Junli Wang, Koichi Motoyama, Christopher J. Penny, Lawrence A. Clevenger
  • Patent number: 11177268
    Abstract: A memory device includes a substrate, a transistor, and a memory cell. The substrate includes a cell region and a logic region. The transistor is over the logic region and includes a first metal gate stack. The memory cell is over the cell region and includes an erase gate. The erase gate is a metal gate stack.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: November 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Cheng Wu, Chien-Hung Chang
  • Patent number: 11177394
    Abstract: A switching device including: a body of semiconductor material, which has a first conductivity type and is delimited by a front surface; a contact layer of a first conductive material, which extends in contact with the front surface; and a plurality of buried regions, which have a second conductivity type and are arranged within the semiconductor body, at a distance from the contact layer.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: November 16, 2021
    Assignee: STMicroelectronics S.r.l.
    Inventors: Mario Giuseppe Saggio, Simone Rascuna'
  • Patent number: 11177275
    Abstract: Provided herein are a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes an etch stop pattern having a top surface and a sidewall disposed over a gate stack having interlayer insulating layers alternately stacked with conductive patterns. The semiconductor device also includes a plurality of channel structures passing through the etch stop pattern and the gate stack. The semiconductor device further includes an insulating layer extending to cover the top surface and the sidewall of the etch stop pattern, wherein a depression is included in a sidewall of the insulating layer. The semiconductor device additionally includes a contact plug passing through the insulating layer so that the contact plug is coupled to a channel structure of the plurality of channel structures.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: November 16, 2021
    Assignee: SK hynix Inc.
    Inventor: Jin Won Lee
  • Patent number: 11171199
    Abstract: The present disclosure relates to an apparatus that includes a bottom electrode and a dielectric structure. The dielectric structure includes a first dielectric layer on the bottom electrode and the first dielectric layer has a first thickness. The apparatus also includes a blocking layer on the first dielectric layer and a second dielectric layer on the blocking layer. The second dielectric layer has a second thickness that is less than the first thickness. The apparatus further includes a top electrode over the dielectric structure.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: November 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Ting Chen, Tsung-Han Tsai, Kun-Tsang Chuang, Po-Jen Wang, Ying-Hao Chen, Chien-Cheng Huang
  • Patent number: 11171260
    Abstract: A light-emitting device includes: a mounting board; at least one light-emitting element located on or above the mounting board; a first covering member comprising, in order from an upper surface of the mounting board: a containing layer comprising a light-absorbing material, and a light-transmissive layer; and a second covering member over the first covering member and the light-emitting element. A thickness of the containing layer is less than a thickness of the light-emitting element.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: November 9, 2021
    Assignee: NICHIA CORPORATION
    Inventors: Kenji Ozeki, Atsushi Kojima, Chinami Nakai, Yoshio Ichihara
  • Patent number: 11164928
    Abstract: Provided is a flexible organic electroluminescent device and a method for fabricating the same. In the flexible electroluminescent device, line hole patterns are formed on surfaces of a plurality of inorganic layers positioned in a pad region in which a flexible printed circuit board is connected to prevent a path of cracks caused by repeated bending and spreading of the organic electroluminescent device from spreading to the interior of the device.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: November 2, 2021
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Su Ho Kim, Sang Bae Kim, Jun Tae Jeon, Yong Sam Lee
  • Patent number: 11165033
    Abstract: An active device is disposed on a substrate and includes a gate, an organic active layer, a gate insulation layer, a plurality of crystal induced structures, a source and a drain. The gate insulation layer is disposed between the gate and the organic active layer. The crystal induced structures distribute in the organic active layer and directly contact with the substrate or the gate insulation layer. The source and the drain are disposed on two opposite sides of the organic active layer, wherein a portion of the organic active layer is exposed between the source and the drain.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: November 2, 2021
    Assignee: E Ink Holdings Inc.
    Inventors: Hsiao-Wen Zan, Chuang-Chuang Tsai, Chao-Hsuan Chen, Cheng-Hang Hsu
  • Patent number: 11158589
    Abstract: A semiconductor device has a semiconductor chip region which contains a semiconductor chip and a first portion of a passivation film covering the semiconductor chip and a scribe line region which contains a second portion of the passivation film connected to the first portion of the passivation film, a first insulating film protruding from a distal end of the second portion of the passivation film, and at least a part of a first wiring. A first portion of the first insulating film is disposed along the distal end of the second portion of the passivation film, a second portion of the first insulating film protrudes laterally beyond the first portion of the first insulating film, and the first wiring protrudes laterally beyond the second portion of the first insulating film.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: October 26, 2021
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Seung Hun Han, Yun Rae Cho, Nam Gyu Baek, Ae Nee Jang
  • Patent number: 11152380
    Abstract: A memory device may include a first conductivity region, and second and third conductivity regions arranged at least partially within the first conductivity region. The first and second conductivity regions may have a different conductivity type from at least a part of the third conductivity region. The memory device may include first and second gates arranged over the third conductivity region. The second conductivity region may be coupled to a source line, and the gates may be coupled to respective word lines. When a predetermined write voltage difference is applied between the source line and a word line, an oxide layer of the gate coupled to the word line may break down to form a conductive link between the gate electrode of the gate and the third conductivity region. The memory device may have a smaller cell area, and may be capable of operating at both higher and lower voltages.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: October 19, 2021
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Desmond Jia Jun Loy, Eng Huat Toh, Bin Liu, Shyue Seng Tan
  • Patent number: 11152483
    Abstract: According to some embodiments, a method for stabilizing electrical properties of a diamond semiconductor comprises terminating a surface of a diamond with hydrogen (H) or deuterium (D) atoms and over-coating the surface of the diamond with an encapsulating material comprising metal oxide salt doped with one or more elements capable of generating negative charge in the metal oxide salt.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: October 19, 2021
    Assignee: Massachusetts Institute of Technology
    Inventors: Michael Geis, Joseph Varghese, Robert Nemanich
  • Patent number: 11152552
    Abstract: A light emitting device includes a substrate, a light emitting element, and a frame. The substrate has a base and a wiring component. The frame surrounds the light emitting element on the substrate and has an inner edge and an outer edge. The wiring component has a first wiring layer constituting at least a part of an outermost surface of the wiring component inside of the outer edge of the frame, and connected to the light emitting element, and a second wiring layer constituting at least a part of the outermost surface of the wiring component outside of the inner edge of the frame, and made from a different material from the first wiring layer. A boundary between the first wiring layer and the second wiring layer on the outermost surface of the wiring component is disposed inside the outer edge of the frame.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: October 19, 2021
    Assignee: NICHIA CORPORATION
    Inventor: Hiroki Nakai
  • Patent number: 11145750
    Abstract: A semiconductor device comprises a fin structure disposed over a substrate; a gate structure disposed over part of the fin structure; a source/drain structure, which includes part of the fin structure not covered by the gate structure; an interlayer dielectric layer formed over the fin structure, the gate structure, and the source/drain structure; a contact hole formed in the interlayer dielectric layer; and a contact material disposed in the contact hole. The fin structure extends in a first direction and includes an upper layer, wherein a part of the upper layer is exposed from an isolation insulating layer. The gate structure extends in a second direction perpendicular to the first direction. The contact material includes a silicon phosphide layer and a metal layer.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: October 12, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Yi Peng, Chih Chieh Yeh, Chih-Sheng Chang, Hung-Li Chiang, Hung-Ming Chen, Yee-Chia Yeo
  • Patent number: 11139449
    Abstract: A resin composition for sealing an organic electronic device element, containing a polyisobutylene resin (A), a hydrogenated cyclic olefin resin (B), and a polymer (C) obtained by any one of radical polymerization, anionic polymerization or coordination polymerization and exhibiting rubber elasticity, a resin sheet using the same, organic electroluminescent element, and image display apparatus.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: October 5, 2021
    Assignee: FURUKAWA ELECTRIC CO., LTD.
    Inventors: Tetsuya Mieda, Kunihiko Ishiguro
  • Patent number: 11139253
    Abstract: A semiconductor package is provided. The semiconductor package comprises a first substrate, a second substrate disposed on the first substrate, a first semiconductor chip disposed on the second substrate, and a stiffener extending from an upper surface of the first substrate to an upper surface of the second substrate, the stiffener not being in contact with the first semiconductor chip, wherein a first height from the upper surface of the first substrate to an upper surface of the first semiconductor chip is greater than a second height from the upper surface of the first substrate to an uppermost surface of the stiffener.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: October 5, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chui Woo Kim, Sang Min Yong, Yang Gyoo Jung
  • Patent number: 11133363
    Abstract: The present discloses an array substrate and a manufacturing method thereof, and a display device. The array substrate includes a first transistor and a second transistor. The first transistor includes a first active layer, a first gate, a first source and a first drain. The second transistor includes a second active layer, a second gate, a second source and a second drain. An orthographic projection of the second source on the base substrate and an orthographic projection of the second drain on the base substrate at least partially overlap. One of the second source and the second drain is in the same layer as and made from the same material as the first gate. The first source and the first drain are in the same layer as and made from the same material as the other of the second source and the second drain.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: September 28, 2021
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Ke Wang, Xinhong Lu, Hehe Hu, Wei Yang, Ce Ning
  • Patent number: 11133460
    Abstract: Embodiments of the disclosure provide methods and apparatus for fabricating magnetic tunnel junction (MTJ) structures on a substrate in for spin-transfer-torque magnetoresistive random access memory (STT-MRAM) applications. In one example, a film stack utilized to form a magnetic tunnel junction structure on a substrate includes a pinned layer disposed on a substrate, wherein the pinned layer comprises multiple layers including at least one or more of a Co containing layer, Pt containing layer, Ta containing layer, an Ru containing layer, an optional structure decoupling layer disposed on the pinned magnetic layer, a magnetic reference layer disposed on the optional structure decoupling layer, a tunneling barrier layer disposed on the magnetic reference layer, a magnetic storage layer disposed on the tunneling barrier layer, and a capping layer disposed on the magnetic storage layer.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: September 28, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Lin Xue, Jaesoo Ahn, Mahendra Pakala, Chi Hong Ching, Rongjun Wang
  • Patent number: 11127629
    Abstract: A method of fabricating a semiconductor device includes: forming a trench on an insulating layer to expose a first conductive feature disposed under the insulating layer; forming a barrier layer over the insulating layer, a sidewall of the trench, and the first conductive feature; etching a bottom of the barrier layer to expose the first conductive feature; and forming a second conductive feature over an exposed portion of the first conductive feature.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: September 21, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Su-Horng Lin
  • Patent number: 11121306
    Abstract: Provided are a magnetic tunnel junction device and a method of fabricating the same. The magnetic tunnel junction device includes a heavy metal layer, a free magnetic layer disposed on the heavy metal layer, and a tunnel insulating layer disposed on the free magnetic layer. The heavy metal layer includes platinum (Pt), the free magnetic layer includes cobalt (Co), a magnetization state of the free magnetic layer has an easy-cone state, the free magnetic layer has a positive first-order perpendicular magnetic anisotropy constant and a negative second-order perpendicular magnetic anisotropy constant, and the tunnel insulating layer includes magnesium oxide (MgO).
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: September 14, 2021
    Assignee: Korea University Research and Business Foundation
    Inventors: Sang Ho Lim, Hyung-Keun Gweon, Seong Rae Lee
  • Patent number: 11121284
    Abstract: Disclosed in an embodiment is a semiconductor device comprising: a light-emitting structure including a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer disposed between the first conductive semiconductor layer and the second conductive semiconductor layer; a first electrode electrically connected to the first conductive semiconductor layer; a second electrode electrically connected to the second conductive semiconductor layer; a reflective layer disposed on the second electrode and including a first metal; and a nitride of the first metal between the second electrode and the reflective layer.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: September 14, 2021
    Assignee: SUZHOU LEKIN SEMICONDUCTOR CO., LTD.
    Inventors: Ki Man Kang, Eun Dk Lee, Hyun Soo Lim, Youn Joon Sung