Abstract: The present disclosure discloses a display apparatus, including a substrate including a pixel area including a disconnected area which encloses a hole area, an organic light emitting diode formed in the pixel area and the disconnected area, a plurality of inorganic insulating layers disposed below the organic light emitting diode, a disconnection structure which is disposed in the disconnected area and encloses the hole area, and an internal dam which is disposed in the disconnected area and encloses the disconnection structure, and in which the disconnection structure includes an eave portion which is simultaneously formed with the internal dam and a trench which is formed by etching the plurality of inorganic insulating layers disposed below the eave portion, and the disconnection structure is configured to have a predetermined overhang and a predetermined depth by the eave portion and the trench structure.

Abstract: Provided are an organic light-emitting panel and an organic light-emitting display device including the same. In the organic light-emitting panel, a planarization layer has at least one contact holes in an active area, and first inclination of a first side surface of the planarization layer, located in the non-active area and closest to a dam, with respect to the top surface of the substrate is smaller than a second inclination of a second side surface of the planarization layer, surrounding the contact hole, with respect to the top surface of the substrate.

Abstract: A transistor structure includes a gate structure, a channel region, a drain region and a source region. The gate structure is positioned above a silicon surface of a first silicon material, the channel region is under the silicon surface, and the channel region includes a first terminal and a second terminal. The drain/source region is independent and not derived from the first silicon material, the drain region includes a first predetermined physical boundary directly connected to the first terminal of the channel region, and the source region includes a second predetermined physical boundary directly connected to the second terminal of the channel region. The drain/source region includes a lower portion below the silicon surface and the bottom of the lower portion of the drain/source region is confined to an isolator, and sidewalls of the drain/source region are confined to spacers except sidewalls of the lower portion of the drain/source region.

Abstract: A display device includes: a substrate including an opening area, a peripheral area surrounding the opening area, and a display area surrounding the peripheral area; a transistor overlapping the display area and disposed on the substrate; a first electrode electrically connected to the transistor; an intermediate layer and a second electrode disposed on the first electrode and extending to the peripheral area; and a metal layer overlapping the intermediate layer and the second electrode in the peripheral area, wherein an end of the first metal layer and an end of the second electrode are aligned, and an end of the intermediate layer is protruded more than the end of the first metal layer.

Abstract: Provided herein are a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes an etch stop pattern having a top surface and a sidewall disposed over a gate stack having interlayer insulating layers alternately stacked with conductive patterns. The semiconductor device also includes a plurality of channel structures passing through the etch stop pattern and the gate stack. The semiconductor device further includes an insulating layer extending to cover the top surface and the sidewall of the etch stop pattern, wherein a depression is included in a sidewall of the insulating layer. The semiconductor device additionally includes a contact plug passing through the insulating layer so that the contact plug is coupled to a channel structure of the plurality of channel structures.

Abstract: A display device includes a substrate having a display area and a non-display area, a pixel electrode, an organic emissive layer, a common electrode, a first inorganic encapsulation layer, an organic encapsulation layer, a second inorganic encapsulation layer, a dam, a bank disposed closer to a peripheral edge of the substrate than the dam, an inorganic encapsulation area, wherein the first inorganic encapsulation layer contacts the second inorganic encapsulation layer in the inorganic encapsulation area, and a first voltage supply line in a bank area where the bank is disposed, and in the inorganic encapsulation area. The first voltage supply line includes a plurality of anti-moisture patterns protruding from one side of the first subsidiary voltage supply line and having at least one of a length and a width in the inorganic encapsulation area respectively different from those of the plurality of anti-moisture patterns in the bank area.

Abstract: A semiconductor device comprises a fin structure disposed over a substrate; a gate structure disposed over part of the fin structure; a source/drain structure, which includes part of the fin structure not covered by the gate structure; an interlayer dielectric layer formed over the fin structure, the gate structure, and the source/drain structure; a contact hole formed in the interlayer dielectric layer; and a contact material disposed in the contact hole. The fin structure extends in a first direction and includes an upper layer, wherein a part of the upper layer is exposed from an isolation insulating layer. The gate structure extends in a second direction perpendicular to the first direction. The contact material includes a silicon phosphide layer and a metal layer.

Abstract: An organic light emitting diode display according to an exemplary embodiment includes: a substrate; a first buffer layer on the substrate; a first semiconductor layer on the first buffer layer; a first gate insulating layer on the first semiconductor layer; a first gate electrode and a blocking layer on the first gate insulating layer; a second buffer layer on the first gate electrode; a second semiconductor layer on the second buffer layer; a second gate insulating layer on the second semiconductor layer; and a second gate electrode on the second gate insulating layer.

Abstract: A display device includes a first layer having a display area including pixels and a non-display area surrounding the display area; a second layer disposed on the first layer and including an intermediate inorganic film and an intermediate organic film; a third layer disposed on the second layer and including display elements; a first dam structure disposed outside an edge of the intermediate organic film and extending along the edge of the intermediate organic film; a fourth layer including first and second encapsulation inorganic films; a fifth layer in disposed on the fourth layer; a sixth layer disposed on the fifth layer and including a light blocking layer, a plurality of color filters, and a seventh layer covering the light blocking layer and the plurality of color filters; and a second dam structure disposed on the non-display area and defining a boundary of the seventh layer.

Abstract: A display panel includes: a substrate including a front display area, where a first display element is in the front display area, a first side display area connected in a first direction to the front display area, a second side display area connected in a second direction to the front display area, a corner display area between the first side display area and the second side display area, where a second display element is in the corner display area, an intermediate display area located between the front display area and the corner display area, where a third display element is in the intermediate display area, and a groove is defined on the substrate; and an inorganic pattern layer on opposing sides of the groove and including a pair of protruding tips protruding toward a center of the groove, where the groove is between the second and third display elements.

Abstract: Provided is a flexible organic electroluminescent device and a method for fabricating the same. In the flexible electroluminescent device, line hole patterns are formed on surfaces of a plurality of inorganic layers positioned in a pad region in which a flexible printed circuit board is connected to prevent a path of cracks caused by repeated bending and spreading of the organic electroluminescent device from spreading to the interior of the device.

Abstract: An organic light-emitting display apparatus is provided as follows. A thin film transistor is disposed on a substrate. A first insulating layer covers the thin film transistor. The first insulating layer includes a barrier wall and a flat portion. The barrier wall protrudes from the flat portion. A pixel electrode is disposed on the flat portion surrounded by the barrier wall. The pixel electrode is electrically connected to the thin film transistor. A pixel defining layer is disposed on the pixel electrode and partially exposes the pixel electrode.

Abstract: Provided is a display device including a first substrate including a display part and a non-display part around the display part, a second substrate disposed on the first substrate, a pixel disposed between the display part and the second substrate, a quantum dot layer disposed between the second substrate and the pixel, a bank layer disposed around the quantum dot layer, and when viewed on a plane, overlapping the non-display part, a color filter disposed between the second substrate and the quantum dot layer, a dummy color filter, when viewed on the plane, overlapping the non-display part, and disposed between the bank layer and the second substrate, and a sealant disposed between the non-display part and the bank layer.

Abstract: A display device includes a display panel including an active area and a non-active area surrounding the active area; a front cover disposed in an upper portion of the display panel; a back cover disposed in a lower portion of the display panel; a dam disposed to surround an outer periphery of the active area in the non-active area of the display panel; a pad area spaced apart from the dam in the non-active area and disposed in an edge of one side of the non-active area; at least one inspection line spaced apart from the dam in the non-active area and disposed to surround a portion of an outer periphery of the dam; and at least one align mark integral with the inspection line.

Abstract: Disclosed herein is a new and improved system and method for fabricating diamond semiconductors. The system may include a diamond malarial having n-type donor atoms and a diamond lattice, wherein 0.16% of the donor atoms contribute conduction electrons with mobility greater than 770 cm2/Vs to the diamond lattice at 100 kPa and 300K. The method of fabricating diamond semiconductors may include the steps of selecting a diamond material having a diamond lattice; introducing a minimal amount of acceptor dopant atoms to the diamond lattice to create ion tracks; introducing substitutional dopant atoms to the diamond lattice through the ion tracks; and annealing the diamond lattice.

Abstract: The present technology relates to an imaging device, an electronic apparatus, and a method of manufacturing an imaging device capable of thinning a semiconductor on a terminal extraction surface while maintaining a strength of a semiconductor chip. There is provided an imaging device including: a first substrate having a pixel region in which pixels are two-dimensionally arranged, the pixels performing photoelectric conversion of light; and a second substrate in which a through silicon via is formed, in which a dug portion is formed in a back surface of the second substrate opposite to an incident side of light of the second substrate, and a redistribution layer (RDL) connected to a back surface of the first substrate is formed in the dug portion. The present technology can be applied to, for example, a semiconductor package including a semiconductor chip.

Abstract: A semiconductor device includes an active fin extending in a first direction on a substrate, a gate electrode intersecting the active fin and extending in a second direction, source/drain regions disposed on the active fin on both sides of the gate electrode, and a contact plug disposed on the source/drain regions. The contact plug has at least one side extending in the second direction which has a step portion having a step shape.

Abstract: A display device includes: a display including a plurality of light-emitting devices; a first bank provided outside the display; a second bank provided outside the first bank; and a plurality of peripheral lines formed below, and intersecting with, the first bank and the second bank, wherein each of the peripheral lines includes a plurality of bends provided between the first bank and the second bank in plan view.

Abstract: A display device includes a first substrate including a display area in which a plurality of pixels are arranged and a light transmitting area disposed in the display area, an interlayer insulating layer covering the display area and exposing the light transmitting area, an inner sidewall of the interlayer insulating layer defining the light transmitting area, and an inorganic film disposed directly on the first substrate in the light transmitting area and overlapping the entire light transmitting area. A size of the light transmitting area is larger than a size of a pixel of the plurality of pixels.

Abstract: Embodiments include semiconductor packages. A semiconductor package includes a plurality of dies on a package substrate, and a plurality of smart dies on the package substrate, where the plurality of smart dies include a plurality of interconnects and a plurality of capacitors. The semiconductor package also includes a plurality of routing lines coupled to the dies and the smart dies, where the routing lines are communicatively coupled to the interconnects of the smart dies, where each of the dies has at least two or more routing lines to communicatively couple the dies together, and where one of the routing lines is via the interconnects of the smart dies. The capacitors may be a plurality of metal-insulator-metal (MIM) capacitors. The dies may be a plurality of active dies. The routing lines may communicatively couple first and second active dies to first and second smart dies.