Patents Examined by Vu Vu
  • Patent number: 11948911
    Abstract: The present disclosure provides a semiconductor packaging method and a semiconductor package device. The semiconductor packaging method includes providing a chip, where the chip includes a chip substrate having a front surface and a back surface, where the front surface includes a photosensitive region; soldering pads disposed at the front surface of the chip substrate surrounding the photosensitive region; a metal part formed on a side of each soldering pad facing away from the chip substrate; and a transparent protective layer formed on the front surface of the chip substrate, where a first end of the metal part is exposed by protruding over a surface of the transparent protective layer. The method further includes electrically connecting the first end of the metal part to a circuit board using a conductive connection part, such that the chip is electrically connected to the circuit board.
    Type: Grant
    Filed: May 5, 2021
    Date of Patent: April 2, 2024
    Assignee: TONGFU MICROELECTRONICS CO., LTD.
    Inventor: Guoqing Yu
  • Patent number: 11942352
    Abstract: A manufacturing method of an LED display is disclosed. The method includes picking up a plurality of LED chips spaced apart at a first interval with a stretchable stamp, spacing apart the plurality of LED chips at a second interval by stretching the stretchable stamp, and transferring the plurality of LED chips to a target substrate.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: March 26, 2024
    Assignee: INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
    Inventors: Dahl Young Khang, Byong Joo Lee
  • Patent number: 11942754
    Abstract: The present invention discloses a driving current correction method and apparatus for multiple laser devices, and a laser projector.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: March 26, 2024
    Assignee: GOER OPTICAL TECHNOLOGY CO., LTD.
    Inventors: Lebao Yang, Xianbin Wang
  • Patent number: 11942762
    Abstract: A surface-emitting laser device according to an embodiment comprises: a first electrode; a substrate arranged on the first electrode; a first reflection layer arranged on the substrate; an active region arranged on the first reflection layer and including a cavity; an opening region arranged on the active region and including an aperture and an insulation region; a second reflection layer arranged on the opening region; a second electrode arranged on the second reflection layer; and a delta doping layer arranged in the opening region. The thickness of the insulation region becomes thinner in the direction of the aperture, and the delta doping layer can be arranged at the aperture.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: March 26, 2024
    Assignee: SUZHOU LEKIN SEMICONDUCTOR CO., LTD.
    Inventors: Jeong Sik Lee, Sang Heon Han, Keun Uk Park, Yeo Jae Yoon
  • Patent number: 11941485
    Abstract: A method for producing a quantum device comprising providing a substrate having a front face and carrying at least one transistor pattern on the front face thereof, said transistor pattern comprising, in a stack a gate dielectric on the front face of the substrate, and a gate on the gate dielectric, said gate having a top and sidewalls. The method further includes forming a protective layer at the front face of the substrate, said protective layer being configured to prevent diffusion of at least one metal species in the substrate, forming a metal layer that has, as a main component, at least one metal species, at least on the sidewalls of the gate, said at least one metal species comprising at least one superconducting element, and forming a superconducting region in the gate by lateral diffusion of the at least one superconducting element from the sidewalls of said gate.
    Type: Grant
    Filed: November 24, 2021
    Date of Patent: March 26, 2024
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Nicolas Posseme, Louis Hutin, Cyrille Le Royer, François Lefloch, Fabrice Nemouchi, Maud Vinet
  • Patent number: 11935865
    Abstract: A method for producing a semiconductor package, capable of effectively suppressing contamination of a chemical liquid and unintended peeling-off of a reinforcing sheet, is provided. This method includes providing a tacky sheet including a substrate sheet, and a soluble tacky layer and a banking tacky layer on at least one surface of the substrate sheet; making a first laminate including a redistribution layer; using the tacky sheet to obtain a second laminate having a second support substrate bonded to a surface on the redistribution layer side of the first laminate with the tacky layer therebetween; peeling off the first support substrate, pretreating the resulting third laminate; mounting a semiconductor chip on a pretreated surface of the redistribution layer; immersing the third laminate in a solution to dissolve or soften the tacky layer; and peeling off the second support substrate in a state where the tacky layer is dissolved or softened.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: March 19, 2024
    Assignee: MITSUI MINING & SMELTING CO., LTD.
    Inventors: Toshimi Nakamura, Tetsuro Sato
  • Patent number: 11935777
    Abstract: A semiconductor device is manufactured using a support base and a filling material formed on the support base. The filling material can be a plurality of protrusions or penetrable film. The protrusions are attached to the support base with an adhesive. The protrusions have a variety of shapes such as square frustum, conical frustum, three-sided pyramid with a flat top, four-sided rectangular body, and elongated square frustum. A semiconductor wafer is disposed over the support base with the filling material extending into openings in the semiconductor wafer. The openings in the semiconductor wafer can have slanted sidewalls, or a more complex shape such as ledges and vertical projections. The filling material may substantially fill the openings in the semiconductor wafer. The protrusions may partially fill the openings in the semiconductor wafer. The protrusions occupy at least a center of the openings in the semiconductor wafer.
    Type: Grant
    Filed: December 1, 2021
    Date of Patent: March 19, 2024
    Assignee: STATS ChipPAC Pte Ltd.
    Inventors: HyeonChul Lee, HunTeak Lee, HyunSu Tak, Wanil Lee, InHo Seo
  • Patent number: 11929591
    Abstract: A semiconductor light-emitting device includes a stacked body, a cutout section, and a high-resistance region. The stacked body includes a first conductive-type semiconductor layer, an active layer, and a second conductive-type semiconductor layer in this order and has paired side faces opposed to each other. The cutout section is provided on at least one of the paired side faces of the stacked body and has a bottom face where the first conductive-type semiconductor layer is exposed. The high-resistance region is provided from the vicinity of the bottom face of the cutout section to the side face of the stacked body and has electric resistance higher than the electric resistance of the stacked body in a periphery of the high-resistance region.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: March 12, 2024
    Assignee: SONY CORPORATION
    Inventors: Masahiro Murayama, Takashi Sugiyama
  • Patent number: 11923214
    Abstract: A semiconductor packaging apparatus and methods of manufacturing semiconductor devices using the same. The semiconductor packaging apparatus includes a process unit, and a controller associated with the process unit. The process unit includes a bonding part that bonds a semiconductor substrate and a carrier substrate to each other to form a bonded substrate, a cooling part that cools the bonded substrate, and a detection part in the cooling part and configured to detect a defect of the bonded substrate. The controller is configured to control the process unit using data obtained from the detection part.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: March 5, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Junghyun Cho, Sang-Geun Park, Dongseok Baek, Jaehyuk Choi
  • Patent number: 11923659
    Abstract: A method for controlling a wavelength of an optical module, includes: a laser light source unit emitting a laser beam; a wavelength filter having a periodical transmission characteristic with respect to a wavelength of light; a temperature controller on which the wavelength filter is placed and that adjusting a temperature of the wavelength filter; a heat generating body placed on the temperature controller; and a control device controlling the wavelength of the laser beam emitted from the laser light source unit and control the transmission characteristic of the wavelength filter based on an intensity of the laser beam transmitted through the wavelength filter, the method including changing at least one of a target value of the wavelength control of the laser beam and a target value of the control of the wavelength filter based on a current value of the heat generating body.
    Type: Grant
    Filed: August 12, 2020
    Date of Patent: March 5, 2024
    Assignee: FURUKAWA ELECTRIC CO., LTD.
    Inventors: Masayoshi Nishita, Atsushi Yamamoto
  • Patent number: 11916022
    Abstract: Various embodiments of the present disclosure are directed towards a semiconductor processing system including an overlay (OVL) shift measurement device. The OVL shift measurement device is configured to determine an OVL shift between a first wafer and a second wafer, where the second wafer overlies the first wafer. A photolithography device is configured to perform one or more photolithography processes on the second wafer. A controller is configured to perform an alignment process on the photolithography device according to the determined OVL shift. The photolithography device performs the one or more photolithography processes based on the OVL shift.
    Type: Grant
    Filed: June 7, 2022
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yeong-Jyh Lin, Ching I Li, De-Yang Chiou, Sz-Fan Chen, Han-Jui Hu, Ching-Hung Wang, Ru-Liang Lee, Chung-Yi Yu
  • Patent number: 11915925
    Abstract: An object of the present invention is to provide a technique suitable for achieving low wiring resistance and reducing a variation in the resistance value between semiconductor elements to be multilayered in a method of manufacturing a semiconductor device in which the semiconductor elements are multilayered through laminating semiconductor wafers via an adhesive layer. The method of the present invention includes first to third processes. In the first process, a wafer laminate Y is prepared, the wafer laminate Y having a laminated structure including a wafer 3, wafers 1T with a thickness from 1 to 20 um, and an adhesive layer 4 with a thickness from 0.5 to 4.5 ?m interposed between a main surface 3a of the wafer 3 and a back surface 1b of the wafer 1T. In the second process, holes extending from the main surface 1a of the wafer 1T and reaching a wiring pattern of the wafer 3 are formed by a predetermined etching treatment.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: February 27, 2024
    Assignee: DAICEL CORPORATION
    Inventor: Naoko Tsuji
  • Patent number: 11909174
    Abstract: A reflection filter device includes: a ring resonator filter including a ring-shaped waveguide and two arms, each of the two arms being optically coupled to the ring-shaped waveguide; and a dual-branch portion including a light input/output port and two branch ports, the light input/output port being configured to allow input and output of light, the two branch ports being configured to allow output of the light input from the light input/output port, the light being split into two, the two arms being connected to the two branch ports, respectively, at least one of the two arms being equipped with a phase adjuster.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: February 20, 2024
    Assignee: FURUKAWA ELECTRIC CO., LTD.
    Inventors: Yasumasa Kawakita, Yasutaka Higa
  • Patent number: 11908741
    Abstract: The present invention provides a method for an improved protective coating for plasma dicing a substrate. A work piece having a support film, a frame and the substrate, the substrate having a top surface and a bottom surface, the top surface of the substrate having a plurality of device structures and a plurality of street areas is provided. The work piece is formed by adhering the substrate to a support film and then mounting the substrate with the support film to a frame. A composite material coating having a matrix component and a filler component is applied to the top surface of the substrate. The filler component has a plurality of particles. The composite material coating is removed from at least one street area to expose the street area. The exposed street area is plasma etched. The composite material coating is removed from the top surface of the substrate.
    Type: Grant
    Filed: January 24, 2023
    Date of Patent: February 20, 2024
    Assignee: Plasma-Therm LLC
    Inventor: Russell Westerman
  • Patent number: 11909173
    Abstract: A waveguide based wavelength-tunable laser formed on a semiconductor substrate includes a first reflector from which laser light is output, a second reflector configuring a laser resonator together with the first reflector, a gain portion that is provided between the first reflector and the second reflector, at least two wavelength filters that can adjust wavelength characteristics and adjust a wavelength of the laser light, and a phase adjuster that adjusts an optical path length in the laser resonator, and a waveguide is formed to fold back an optical path by an angle of substantially 180 degrees between the first reflector and the second reflector.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: February 20, 2024
    Assignee: FURUKAWA ELECTRIC CO., LTD.
    Inventor: Kazuaki Kiyota
  • Patent number: 11908689
    Abstract: The present application discloses a method, a system, a device, and a storage medium for fabricating a GaN chip. The method includes: growing a Nb2N sacrificial layer on an original substrate, and growing a GaN insertion layer on the Nb2N sacrificial layer; growing a Ta2N sacrificial layer on the GaN insertion layer, and growing a semiconductor layer on the Ta2N sacrificial layer to form a GaN wafer; bonding the GaN wafer with a first surface of a temporary carrier, and removing the Nb2N sacrificial layer and the Ta2N sacrificial layer; and transferring remaining material after removal of the Nb2N sacrificial layer and the Ta2N sacrificial layer to a target substrate, and removing the temporary carrier from the remaining material to form the GaN chip.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: February 20, 2024
    Assignee: INSPUR SUZHOU INTELLIGENT TECHNOLOGY CO., LTD.
    Inventors: Fen Guo, Kang Su, Lang Zhou, Tuo Li, Hongtao Man
  • Patent number: 11908723
    Abstract: Handler wafers and methods of handling a wafer include positioning a handler, which is attached to a wafer by a bonding layer that comprises a debonding layer, an optical enhancement layer, and an anti-reflection layer. The handler is debonded from the wafer using a laser that emits laser energy at a wavelength that is absorbed by the debonding layer and that is confined to the debonding layer by the optical enhancement layer, such that the material of the debonding layer ablates when exposed to the laser energy to release the wafer.
    Type: Grant
    Filed: December 3, 2021
    Date of Patent: February 20, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Akihiro Horibe, Qianwen Chen, Risa Miyazawa, Michael P. Belyansky, John Knickerbocker, Takashi Hisada
  • Patent number: 11901332
    Abstract: A semiconductor device structure and a method for manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a method for manufacturing a semiconductor device that comprises ordering and performing processing steps in a manner that prevents warpage deformation from occurring to a wafer and/or die due to mismatching thermal coefficients.
    Type: Grant
    Filed: June 7, 2021
    Date of Patent: February 13, 2024
    Assignee: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE. LTD.
    Inventors: Yeong Beom Ko, Jin Han Kim, Dong Jin Kim, Do Hyung Kim, Glenn Rinne
  • Patent number: 11901205
    Abstract: Purge diffusers for use in systems for transporting substrates include: i) a purge diffuser core having an internal purge gas channel, one or more diffuser ports and an outer surface; ii) filter media secured to the outer surface of the purge diffuser core; and iii) a purge port connector for mounting the purge diffuser to a purge port of a substrate container for transporting substrates. The purge diffuser core may be a unitary article, may be formed by injection molding, and may include diverters internal to the internal purge gas channel.
    Type: Grant
    Filed: February 14, 2023
    Date of Patent: February 13, 2024
    Assignee: ENTEGRIS, INC.
    Inventors: Mark V. Smith, Nicholas Thelen, Matthew A. Fuller, Michael C. Zabka, Sung In Moon, John P. Puglia
  • Patent number: 11901333
    Abstract: Embodiments include semiconductor packages and a method to form such semiconductor packages. A semiconductor package includes a plurality of dies on a substrate, and an encapsulation layer over the substrate. The encapsulation layer surrounds the dies. The semiconductor package also includes a plurality of dummy silicon regions on the substrate. The dummy silicon regions surround the dies and encapsulation layer. The plurality of dummy silicon regions are positioned on two or more edges of the substrate. The dummy silicon regions have a top surface substantially coplanar to a top surface of the dies. The dummy silicon regions include materials that include silicon, metals, or highly-thermal conductive materials. The materials have a thermal conductivity of approximately 120 W/mK or greater, or is equal to or greater than the thermal conductivity of silicon. An underfill layer surrounds the substrate and the dies, where the encapsulation layer surrounds portions of the underfill layer.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: February 13, 2024
    Assignee: Intel Corporation
    Inventors: Wei Li, Edvin Cetegen, Nicholas S. Haehn, Ram S. Viswanath, Nicholas Neal, Mitul Modi