Abstract: To prevent the surface of a base substrate and the bottom surface of a separated semiconductor epitaxial layer from being bonded to each other even after a removal layer is removed, the semiconductor substrate includes a base substrate, a first removal layer provided on the base substrate, a second removal layer provided above the first removal layer, and a semiconductor epitaxial layer provided above the second removal layer, and an etching rate of the second removal layer for a predetermined etching material is larger than the etching rate of the first removal layer for the predetermined etching material.

Abstract: The present invention provides a SiP structure and method for a light emitting diode (LED) chip. The packaging structure includes: a heat sink structure, a first chip, a first packaging layer, a second packaging layer, a rewiring layer, an LED chip, a printed circuit board (PCB), and a third packaging layer. In the present invention, chips with a plurality of functions, including the first chip, the LED chip, and the like, are integrated into one packaging structure through fan-out system-level packaging, to meet a plurality of different system functional requirements and improve the performance of the packaging system. By the rewiring layer, a metal connecting pillar, a metal lead wire, and the like, the first chip, the LED chip, and the PCB are electrically connected, to achieve a three-dimensional vertically stacked package thereby effectively reducing the area of a SiP and improving the integration of the packaging system.

Abstract: An H-bridge integrated laser driver optimizes power dissipation, impedance matching, low-swing and high-swing reliability for electro-absorption modulated laser (EML) and directly modulated laser diode (DML) applications. The laser driver includes a retimer for converting low-speed parallel data to a high-speed serial bit stream and to an inverted representation of the high-speed parallel bit stream, an M-bit PMOS DAC configured to receive a first buffered bit stream, an N-bit NMOS DAC configured to receive a second buffered bit stream substantially synchronized with the first buffered bit stream. A protective device is coupled between the M-bit DAC and the N-bit DAC.

Abstract: A light emitting photonic crystal having an organic light emitting diode and methods of making the same are disclosed. An organic light emitting diode disposed within a photonic structure having a band-gap, or stop-band, allows the photonic structure to emit light at wavelengths occurring at the edges of the band-gap. Photonic crystal structures that provide this function may include materials having a refractive index that varies.

Abstract: The present invention relates to a device for selective separating electronic components from a frame with electronic components including at least two press parts; drive means for moving the press parts; a guide for guiding frames between the press parts; a plurality of punches in a first press part and a plurality of openings in a second press part. The invention also provides a system for in-line selective separating electronic components from a frame with electronic components and a method for selective separating electronic components from a frame with electronic components.

Abstract: A laser cleaning method and device for improving uniformity of a laser cleaning surface are provided. The laser cleaning method includes: applying a peaked-top sine wave signal to a motor; controlling a galvanometer to swing in a reciprocated manner by the motor; shaping a laser beam emitted by a laser to a linear beam by the reciprocated swing of the galvanometer; and performing laser cleaning using the shaped linear beam.

Abstract: A laser device for skin treatment includes: a laser generating unit including a diode laser for generating a pulse capable of being varied to a pulse width of 100 picoseconds (ps) to 2000 ps by a dedicated driver having a rising time of 100 ps or less and a pulse width adjustment unit for adjusting a width of the pulse generated by the diode laser, the laser generating unit configured to generate a single or a plurality of pulses; and a laser amplifying unit including a pumping lamp and a single or a plurality of amplification mediums having a rod structure for absorbing light energy from the pumping lamp, wherein, in the laser amplifying unit, a pulse supplied from the laser generating unit passes through at least one of the single or a plurality of amplification mediums a plurality of times inward from the outside and is gradually amplified.

Abstract: Provided is a semiconductor device manufacturing method in which semiconductor elements are formed into multiple layers through the lamination of wafers in which the semiconductor elements are fabricated, the method being suited for efficiently creating multiple layers of thin wafers while suppressing warping of a wafer laminate. The method of the present invention includes a preparation step, a thinning step, a bonding step, a removal step, and a multilayering step. In the preparation step, a reinforced wafer is prepared, the reinforced wafer having a laminated structure that includes: a wafer including an element forming surface and a back surface opposite from the element forming surface; a supporting substrate; and a temporary adhesive layer for forming temporary adhesion, the temporary adhesive layer being provided between the element forming surface side of the wafer and the supporting substrate.

Abstract: In a described example, a method includes: forming a metal layer on a backside surface of a semiconductor wafer, the semiconductor wafer having semiconductor dies spaced apart by scribe lanes on an active surface of the semiconductor wafer opposite the backside surface; forming a layer with a modulus greater than about 4000 MPa up to about 8000 MPa over the metal layer; mounting the backside of the semiconductor wafer on a first side of a dicing tape having an adhesive; cutting through the semiconductor wafer, the metal layer, and the layer with a modulus greater than about 4000 MPa up to about 8000 MPa along scribe lanes; separating the semiconductor dies from the semiconductor wafer and from one another by stretching the dicing tape, expanding the cuts in the semiconductor wafer along the scribe lanes between the semiconductor dies; and removing the separated semiconductor dies from the dicing tape.

Abstract: A semiconductor integrated circuit device including standard cells including fin transistors includes, at a cell row end, a cell-row-terminating cell that does not contribute to a logical function of a circuit block. The cell-row-terminating cell includes a plurality of fins extending in an X direction. Ends of the plurality of fins on the inner side of the circuit block are near a gate structure placed at a cell end and do not overlap with the gate structure in a plan view, and ends of the plurality of fins on an outer side of the circuit block overlap with any one of a gate structure in a plan view.

Abstract: In one example, a semiconductor device comprises a first substrate comprising a first conductive structure, a first body over the first conductive structure and comprising an inner sidewall defining a cavity in the first body, a first interface dielectric over the first body, and a first internal interconnect in the first body and the first interface dielectric, and coupled with the first conductive structure. The semiconductor device further comprises a second substrate over the first substrate and comprising a second interface dielectric, a second body over the second interface dielectric, and a second conductive structure over the second body and comprising a second internal interconnect in the second body and the second interface dielectric. An electronic component is in the cavity, and the second internal interconnect is coupled with the first internal interconnect. Other examples and related methods are also disclosed herein.

Abstract: Techniques and devices are disclosed for forming wettable flanks on no-leads semiconductor packages. A lead frame assembly may include a plurality of leads, each lead including a die surface and a plating surface, and an integrated circuit die arranged on the die surface. The plating surface for each of the leads may be plated with an electrical plating. A connecting film may be applied and lead frame assembly may be singulated into individual semiconductor packages by a series of cuts through each of the plurality of leads and the electrical plating of each of the plurality of leads to a depth up to or through a portion of the connecting film to create a channel exposing lead sidewalls of each of the plurality of leads. The lead sidewalls of each of the plurality of leads may be plated with a second electrical plating and the connecting film may be removed.

Abstract: A method of fabricating a display panel may include forming an oxide semiconductor pattern on a base layer including a first region and a second region, etching first, second, and third insulating layers to form a first groove that overlaps the second region, forming electrodes on the third insulating layer, forming a fourth insulating layer on the third insulating layer to cover the electrodes, thermally treating the fourth insulating layer, forming an organic layer to cover the fourth insulating layer, and forming an organic light emitting diode on the organic layer.

Abstract: A highly thermal conductive substrate formed by bonding a device layer formed on a silicon on insulator (SOI) wafer and a buried oxide film to an insulator substrate having a thermal conductivity of 40 W/m·K or more via a low-stress adhesive, wherein a thickness of the buried oxide film is 50 to 500 nm and a thickness of the adhesive is 0.1 to 10 ?m.

Abstract: A frequency modulated continuous wave (FMCW) light detection and ranging (LIDAR) system that includes an optical source to generate light at a target frequency. The system also includes a first transistor to transmit a modulation current through a modulation path that includes the optical source and a modulation resistor. The system also includes electro optical circuitry coupled to the first transistor to produce a phase locked loop. The system also includes a second transistor to transmit a bias current through a bias path that includes the optical source and is separate from the modulation path, wherein the bias path is separate from the modulation path.

Abstract: A light emitting display device includes a lower substrate, a driving transistor positioned on the lower substrate and including a semiconductor layer, a gate electrode, a source electrode, and a drain electrode, and a light shield layer covering a lower surface, an upper surface, and a side surface of the semiconductor layer, for protecting the driving transistor from external light.

Abstract: A semiconductor device has a semiconductor package including a substrate with a land grid array. A component is disposed over the substrate. An encapsulant is deposited over the component. The land grid array remains outside the encapsulant. A metal mask having a fiducial marker is disposed over the land grid array. A shielding layer is formed over the semiconductor package. The metal mask is removed after forming the shielding layer.

Abstract: A wafer manufacturing method includes a wafer preparing step of preparing a wafer including a semiconductor device formed in each of a plurality of regions demarcated by a plurality of streets intersecting each other, a removing step of separating, from the wafer, a defective device region including a semiconductor device determined to be a defective product among a plurality of the semiconductor devices formed in the wafer, and a fitting step of fitting, into a through hole formed by separating the defective device region from the wafer, a device chip including a semiconductor device as a non-defective product having same functions as those of the semiconductor device determined to be a defective product and having a size capable of being fitted into the through hole.

Abstract: Semiconductor processing apparatuses and methods are provided in which an electrostatic discharge (ESD) prevention layer is utilized to prevent or reduce ESD events from occurring between a semiconductor wafer and one or more components of the apparatuses. In some embodiments, a semiconductor processing apparatus includes a wafer handling structure that is configured to support a semiconductor wafer during processing of the semiconductor wafer. The apparatus further includes an ESD prevention layer on the wafer handling structure. The ESD prevention layer includes a first material and a second material, and the second material has an electrical conductivity that is greater than an electrical conductivity of the first material.

Abstract: Methods of ion implantation combined with annealing using a pulsed laser or a furnace for cutting substrate in forming semiconductor devices and semiconductor devices including the same are disclosed. In an embodiment, a method includes forming a transistor structure of a device on a first semiconductor substrate; forming a front-side interconnect structure over a front side of the transistor structure; bonding a carrier substrate to the front-side interconnect structure; implanting ions into the first semiconductor substrate to form an implantation region of the first semiconductor substrate; and removing the first semiconductor substrate. Removing the first semiconductor substrate includes applying an annealing process to separate the implantation region from a remainder region of the first semiconductor substrate. The method also includes forming a back-side interconnect structure over a back side of the transistor structure.