Abstract: A method of fabricating an integrated fan-out package is provided. A ring-shaped dummy die and a group of integrated circuit dies are mounted over a carrier, wherein the group of integrated circuit dies are surrounded by the ring-shaped dummy die. The ring-shaped dummy die and the group of integrated circuit dies over the carrier are encapsulated with an insulating encapsulation. A redistribution circuit structure is formed on the ring-shaped dummy die, the group of integrated circuit dies and the insulating encapsulation, wherein the redistribution circuit structure is electrically connected to the group of integrated circuit dies, and the ring-shaped dummy die is electrically floating.

Abstract: An object is to provide a technique capable of suppressing defectives in semiconductor elements. A manufacturing method of a semiconductor device includes a step of forming a laminated body in which an adhesive protective layer, an adhesive layer, a peeling layer, and a support substrate are disposed in this order on a first main surface of the semiconductor substrate, a step of removing the semiconductor substrate other than a portion where a plurality of circuit elements are formed, a step of bonding the portion where the circuit elements are formed to a transfer substrate, a step of removing the peeling layer, the support substrate and the adhesive layer, a step of removing the adhesive protective layer by chemical treatment, and a step of dividing the plurality of circuit elements.

Abstract: In described examples, a semiconductor wafer with a thermally conductive surface layer comprises a bulk semiconductor layer having a first surface and a second surface, circuitry on the first surface, a metallic layer attached to the first surface or the second surface, and a graphene layer attached to the metallic layer. The first surface opposes the second surface. The metallic layer comprises a transition metal.

Abstract: In one example, a semiconductor device comprises a main substrate having a top side and a bottom side, a first electronic component on the top side of the main substrate, a second electronic component on the bottom side of the main substrate, a substrate structure on the bottom side of the main substrate adjacent to the second electronic component, and an encapsulant structure comprising an encapsulant top portion on the top side of the main substrate and contacting a side of the first electronic component, and an encapsulant bottom portion on the bottom side of the main substrate and contacting a side of the second electronic component and a side of the substrate structure. Other examples and related methods are also disclosed herein.

Abstract: A semiconductor device structure is provided. The structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. The structure also includes a sealing element extending along a sidewall of the gate stack. The sealing element has a first atomic layer and a second atomic layer, and the first atomic layer and the second atomic layer have different atomic concentrations of carbon. The structure further includes a spacer element over the sealing element.

Abstract: A fly-back or boost stage transfers its stored energy to the energy storage capacitor of the fast driver discharge stage in a single event pulse. The charging voltage of a single flyback pulse on the capacitor is measured in real time and, if necessary, the charging current is diverted via a shunt active device or transistor, to ground, thus preventing the storage capacitor from overcharging with the risk of component damage. A series sense resistor is used to determine the presence and amount of the wasted shunt current in order that this current may be minimized by turning down the flyback energy, thus maximizing the overall efficiency.

Abstract: A bonding apparatus includes a holder; a pressing member; and a curvature adjuster. The holder is configured to attract and hold a substrate to be bonded. The pressing member is configured to come into contact with a central portion of the substrate attracted to and held by the holder and press the substrate to allow the central portion of the substrate to be protruded. The curvature adjuster is configured to adjust a curvature of the substrate pressed by the pressing member.

Abstract: A method of manufacturing thin film transistor(s) includes: providing a monocrystalline silicon wafer, the monocrystalline silicon wafer including a first surface and a second surface that are opposite to each other; forming a bubble layer between the first surface and the second surface of the monocrystalline silicon wafer, the bubble layer dividing the monocrystalline silicon wafer into two portions arranged side by side in a direction perpendicular to the second surface, and a portion of the monocrystalline silicon wafer that is located between the bubble layer and the second surface being a monocrystalline silicon film having a target thickness; providing a substrate, and transferring the monocrystalline silicon film onto the substrate by breaking the monocrystalline silicon wafer at the bubble layer; and patterning the monocrystalline silicon film transferred to the substrate to form active layer(s) of the thin film transistor(s).

Abstract: A semiconductor package has central region and peripheral region surrounding central region. The semiconductor package includes dies, encapsulant, and redistribution structure. The dies include functional die and first dummy dies. Functional die is disposed in central region. First dummy dies are disposed in peripheral region. Redistribution structure is disposed on encapsulant over the dies, and is electrically connected to functional die. Vacancy ratio of central region is in the range from 1.01 to 3.00. Vacancy ratio of the peripheral region is in the range from 1.01 to 3.00. Vacancy ratio of central region is a ratio of total area of central region to total area occupied by dies disposed in central region. Vacancy ratio of peripheral region is a ratio of total area of peripheral region to total area occupied by first dummy dies disposed in peripheral region.

Abstract: A thermocompression bonding method for thermocompression bonding a sheet to a workpiece, where the method includes a stacking step of placing the sheet between a flat plate and the workpiece to form a stack in which the sheet is held between the workpiece and an entire surface of the flat plate and a thermocompression bonding step of thermocompression bonding the sheet to the workpiece while planarizing the sheet with the flat plate by heating the sheet and applying an external force to the stack, after performing the stacking step.

Abstract: A laminated element manufacturing method includes a first forming step of forming a first modified region along a line to cut by irradiating a semiconductor substrate of a first wafer with a laser light along the line to cut, a first grinding step of grinding the semiconductor substrate of the first wafer, a bonding step of bonding a circuit layer of a second wafer to the semiconductor substrate of the first wafer, a second forming step of forming a second modified region along the line to cut by irradiating a semiconductor substrate of the second wafer with a laser light along the line to cut, and a second grinding step of grinding the semiconductor substrate of the second wafer.

Abstract: Panel level packaging (PLP) with high positional accuracy of dies. The PLP bonds dies accurately to die bonding regions of an alignment panel. High accuracy is achieved by providing die bonding regions with local alignment marks. Accurate die bonding on the alignment carrier results in a reconstructed wafer with accurate positioning of dies. The dies of the reconstructed wafer can be scanned by a die location check (DLC) scan based on sub-blocks of dies, enabling high DLC throughput. The DLC scan generates a DLC file with coordinate points of sub-blocks of the reconstructed wafer. Also, a laser direct imaging (LDI) file can be generated using sub-block circuit files aligned to the DLC file. The use of sub-block circuit files facilitates high throughput in generating the LDI file with high accuracy due to the reconstructed wafer being formed using the alignment carrier with local alignment marks.

Abstract: Semiconductor device assemblies with solderless interconnects, and associated systems and methods are disclosed. In one embodiment, a semiconductor device assembly includes a first conductive pillar extending from a semiconductor die and a second conductive pillar extending from a substrate. The first conductive pillar may be connected to the second conductive pillar via an intermediary conductive structure formed between the first and second conductive pillars using an electroless plating solution injected therebetween. The first and second conductive pillars and the intermediary conductive structure may include copper as a common primary component, exclusive of an intermetallic compound (IMC) of a soldering process. A first sidewall surface of the first conductive pillar may be misaligned with respect to a corresponding second sidewall surface of the second conductive pillar.

Abstract: A semiconductor package includes a core substrate having a through hole, a first molding member at least partially filling the through hole and covering an upper surface of the core substrate, the first molding member having a cavity within the through hole, a first semiconductor chip on the first molding member on the upper surface of the core substrate, a second semiconductor chip arranged within the cavity, a second molding member on the first molding member and covering the first semiconductor chip, a third molding member filling the cavity and covering the lower surface of the core substrate; first redistribution wirings on the second molding member and electrically connecting first chip pads of the first semiconductor chip and core connection wirings of the core substrate; and second redistribution wirings on the third molding member and electrically connecting second chip pads of the second semiconductor chip and the core connection wirings.

Abstract: A method includes encapsulating a plurality of package components in an encapsulant, and forming a first plurality of redistribution layers over and electrically coupling to the plurality of package components. The first plurality of redistribution layers have a plurality of power/ground pad stacks, with each of the plurality of power/ground pad stacks having a pad in each of the first plurality of redistribution layers. The plurality of power/ground pad stacks include a plurality of power pad stacks, and a plurality of ground pad stacks. At least one second redistribution layer is formed over the first plurality of redistribution layers. The second redistribution layer(s) include power lines and electrical grounding lines electrically connecting to the plurality of power/ground pad stacks.

Abstract: A method includes transferring multiple discrete components from a first substrate to a second substrate, including illuminating multiple regions on a top surface of a dynamic release layer, the dynamic release layer adhering the multiple discrete components to the first substrate, each of the irradiated regions being aligned with a corresponding one of the discrete components. The illuminating induces a plastic deformation in each of the irradiated regions of the dynamic release layer. The plastic deformation causes at least some of the discrete components to be concurrently released from the first substrate.

Abstract: A semiconductor device package includes an embedded plurality of solder balls within an integrated circuit die (ICD) substrate In one embodiment, the integrated circuit die (ICD) substrate has a top surface and a bottom surface, and a plurality of solder balls at least partially embedded in the ICD substrate, where each of the plurality of solder balls comprises an exposed surface that is substantially flat and parallel planar to the bottom surface, and where the exposed surface of each of the plurality of solder balls is disposed in the bottom surface. In certain examples, the apparatuses also include a plurality of integrated circuit dies stacked on the top surface of the ICD substrate.

Abstract: A method for manufacturing a semiconductor device and a semiconductor substrate are provided. A method for manufacturing a semiconductor device includes the steps of forming a bonding layer that bonds a semiconductor thin film to a bonding layer region on a portion of a first substrate with a force weaker than covalent bonding, forming the semiconductor thin film in the bonding layer region and a non-bonding layer region other than the bonding layer region, separating the semiconductor thin film from the first substrate by bonding an organic layer included in a pick-up substrate different from the first substrate to the semiconductor thin film, removing the bonding layer adhered to a peeled surface of the semiconductor thin film separated from the first substrate, and bonding the semiconductor thin film from which the bonding layer has been removed to a second substrate different from the first substrate.

Abstract: Discussed is an assembly substrate used for a display device manufacturing method of mounting semiconductor light-emitting diodes on the assembly substrate at preset positions using electric field and magnetic field. The assembly substrate includes a base portion, a plurality of assembly electrodes on the base portion, a dielectric layer on the base portion to cover the assembly electrodes, a barrier wall on the base portion, and a metal shielding layer on the base portion, wherein the metal shielding layer overlaps the barrier wall.

Abstract: A diaphragm for a piezoelectric micromachined ultrasonic transducer (PMUT) is presented having resonance frequency and bandwidth characteristics which are decoupled from one another into independent variables. Portions of at least the piezoelectric material layer and backside electrode layer are removed in a selected pattern to form structures, such as ribs, in the diaphragm which retains stiffness while reducing overall mass. The patterned structure can be formed by additive, or subtractive, fabrication processes.