Patents Examined by Vuthe Siek
  • Patent number: 10444622
    Abstract: A method for generating masks for manufacturing of a semiconductor structure includes the following steps. First, a design pattern is provided to a processor. The design pattern includes at least one first pattern and at least two second patterns shorter than the first pattern, wherein two of the second patterns are arranged in a line along an extending direction of the patterns. Then, the second patterns are elongated by the processor such that the two second patterns arranged in the line are separated from each other by a distance equal to a minimum space of the design pattern. The design pattern is divided into a first set of patterns and a second set of patterns by the processor. A first mask is generated by the processor based on the first set of patterns. A second mask is generated by the processor based on the second set of patterns.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: October 15, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tsung-Yeh Wu, Chia-Wei Huang, Yung-Feng Cheng
  • Patent number: 10445453
    Abstract: A cell layout includes a first cell having a plurality of first poly lines extending along a first direction, a second cell having a plurality of second poly lines extending along the first direction, and a boundary cell contiguous with the first cell. The first poly lines have a first uniform poly pitch and the second poly lines have a second uniform poly pitch. The second uniform poly pitch is smaller than the first uniform poly pitch. The boundary cell includes n stripes of first dummy poly lines and m stripes of second dummy poly lines extending along the first direction. The first dummy poly lines have the first uniform poly pitch and the second dummy poly lines have the second uniform pitch.
    Type: Grant
    Filed: March 27, 2016
    Date of Patent: October 15, 2019
    Assignee: MEDIATEK INC.
    Inventor: Jen-Hang Yang
  • Patent number: 10442300
    Abstract: A system for facilitating communication between a vehicle and a user includes a vehicle having a rechargeable battery and a communication and control subsystem. The communication and control subsystem is communicatively coupled to the battery to gather and transmit vehicle information, which may include battery information and a vehicle identifier. The system also includes a charging station having a charging station identifier and an electrical coupling between the charging station, a power source, and the vehicle. The electrical coupling is operable to charge the battery and includes a communicative coupling. The control subsystem is operable to receive communications from the user via the communicative coupling.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: October 15, 2019
    Assignee: KLD ENERGY TECHNOLOGIES, INC.
    Inventors: Charles D. Huston, Martyn T. Hunt
  • Patent number: 10445450
    Abstract: In one embodiment, a generating method of drawing data includes generating a pixel map that includes dose amount information on each of pixels obtained by dividing a drawing area on an object into a mesh, extracting, from the pixel map, an island-shaped pixel map which is a group of multiple pixels in which the dose amount information is not zero, determining an order of definition of the dose amount information on the pixels in the island-shaped pixel map, and generating a compressed pixel map including a size of the pixels, information indicating the order of definition, coordinates of a pixel which is first in the order of definition in the island-shaped pixel map, and the dose amount information on the pixels in the island-shaped pixel map, the dose amount information being continuously defined based on the order of definition.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: October 15, 2019
    Assignee: NuFlare Technology, Inc.
    Inventors: Shigehiro Hara, Kenichi Yasui
  • Patent number: 10439568
    Abstract: A transmission amplifier is provided for amplifying the signal in a wire-free transmission system. The transmission amplifier includes a pre-amplifier stage and an amplifier output stage that is coupled to the pre-amplifier stage. The amplifier output stage is configured with gate components and is configured to provide a signal fed in as an amplified output signal on the output side.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: October 8, 2019
    Assignee: Siemens Aktiengesellschaft
    Inventors: Franz Eiermann, Ralph Oppelt
  • Patent number: 10430542
    Abstract: A system for integrated computational element (“ICE”) design optimization and analysis utilizes a genetic algorithm to evolve layer thickness of each fixed ICE structure using a constrained multi-objective merit function. The system outputs a ranked representative group of ICE design candidates that may be used for further fabricability study, ICE combination selection, efficient statistical analysis and/or feature characterization.
    Type: Grant
    Filed: November 9, 2012
    Date of Patent: October 1, 2019
    Assignee: Halliburton Energy Services, Inc.
    Inventors: Dingding Chen, Christopher Michael Jones, David L. Perkins, Li Gao
  • Patent number: 10432008
    Abstract: The present disclosure includes a method of charging a battery. In one embodiment, the method comprises receiving, in a battery charging circuit on an electronic device, an input voltage having a first voltage value from an external power source. The battery charger is configured to produce a charge current having a first current value into the battery. The input current limit and/or duty cycle of the charger is monitored. Control signals may be generated to increase the first voltage value of the input voltage if either (i) the input current limit is activated or (ii) the duty cycle reaches a maximum duty cycle. The charger also receives signals indicating a temperature inside the electronic device and generates control signals to decrease the value of the input voltage when the temperature increases above a threshold temperature.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: October 1, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Christian Sporck, VaraPrasad Arikatla, Shadi Hawawini, Steve Hawley, Thomas O'Brien, Seema Kumar, Aaron Melgar
  • Patent number: 10414646
    Abstract: A method of forming at least one Micro-Electro-Mechanical System (MEMS) includes forming a beam structure and an electrode on an insulator layer, remote from the beam structure. The method further includes forming at least one sacrificial layer over the beam structure, and remote from the electrode. The method further includes forming a lid structure over the at least one sacrificial layer and the electrode. The method further includes providing simultaneously a vent hole through the lid structure to expose the sacrificial layer and to form a partial via over the electrode. The method further includes venting the sacrificial layer to form a cavity. The method further includes sealing the vent hole with material. The method further includes forming a final via in the lid structure to the electrode, through the partial via.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: September 17, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Russell T. Herrin, Jeffrey C. Maling, Anthony K. Stamper
  • Patent number: 10418244
    Abstract: Aspects describing modified self-aligned quadruple patterning (SAQP) processes using cut pattern masks to fabricate integrated circuit (IC) cells with reduced area are disclosed. In one aspect, a modified SAQP process includes disposing multiple mandrels. First spacers are disposed on either side of each mandrel, and second spacers are disposed on either side of each first spacer. A cut pattern mask is disposed over the second spacers and includes openings that expose second spacers corresponding to locations in which voltage rails are to be disposed. The voltage rails are formed by removing the second spacers exposed by the openings in the cut pattern mask, and disposing the voltage rails in the corresponding locations left vacant by removing the second spacers. Routing lines are disposed over routing tracks formed between each set of the remaining second spacers to allow for interconnecting of active devices formed in the IC cell.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: September 17, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Stanley Seungchul Song, Giridhar Nallapati, Periannan Chidambaram
  • Patent number: 10417367
    Abstract: Transient voltage noise, including resistive and reactive noise, causes timing errors at runtime. A heuristic framework, Walking Pads, is introduced to minimize transient voltage violations by optimizing power supply pad placement. It is shown that the steady-state optimal design point differs from the transient optimum, and further noise reduction can be achieved with transient optimization. The methodology significantly reduces voltage violations by balancing the average transient voltage noise of the four branches at each pad site. When pad placement is optimized using a representative stressmark, voltage violations are reduced 46-80% across 11 Parsec benchmarks with respect to the results from IR-drop-optimized pad placement. It is shown that the allocation of on-chip decoupling capacitance significantly influences the optimal locations of pads.
    Type: Grant
    Filed: June 1, 2015
    Date of Patent: September 17, 2019
    Assignee: UNIVERSITY OF VIRGINIA PATENT FOUNDATION
    Inventors: Ke Wang, Kevin Skadron, Mircea R. Stan, Runjie Zhang
  • Patent number: 10409938
    Abstract: According to one embodiment, a method, computer system, and computer program product for creating a plurality of process parameters in a circuit design is provided. The present embodiment of the invention may include receiving one parasitic extraction per layer of a circuit is used to obtain a resistance base factor and a capacitance base factor. The embodiment may further include performing Monte Carlo simulations to determine distributions of capacitance and resistance for each metal layer of the circuit, and creating scalars that scale each of the resistance base factor and the capacitance base factor to a minimum and maximum process limit. Additionally, the embodiment may include defining at least one delay corner using the created scalars, and receiving the results of one or more timing analyses performed using the resistance base factor and the capacitance base factor, and the defined delay corner to determine a delay variability per layer.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: September 10, 2019
    Assignee: International Business Machines Corporation
    Inventors: Eric Foreman, Ning Lu, Jeffrey Hemmett
  • Patent number: 10411485
    Abstract: A battery protection system, comprising: a first protection circuit configured to detect a battery output voltage value and to disconnect the battery output from a load when the output voltage falls below a first threshold; a second protection circuit configured to detect the battery output voltage value and to disconnect the battery output from the load when the output voltage falls below a second threshold, wherein the first threshold is within a tenth of a volt of the second threshold.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: September 10, 2019
    Assignee: Bose Corporation
    Inventors: Xin Li, Christopher Barnes
  • Patent number: 10409317
    Abstract: Aspects of the disclosure are directed to reducing clock-ungating induced voltage droop by determining a maximum frequency value associated with an output clock waveform; modulating a clock frequency of the output clock waveform for a first time duration based on a first programmable mask pattern or a first Boolean function; and determining if either the first programmable mask pattern or the first Boolean function should be changed. In accordance with one aspect, a voltage droop mitigation circuit includes a control logic for receiving an input clock waveform and a clock enable signal waveform and for outputting a gated clock enable signal waveform; a latch coupled to the control logic, the latch for holding a state of the gated clock enable signal waveform and a AND gate coupled to the latch, the AND gate for outputting an output clock waveform.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: September 10, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Martin Saint-Laurent, Lam Ho, Carlos Andres Rodriguez Ancer, Bhavin Shah
  • Patent number: 10410831
    Abstract: To irradiate a target with a beam of energetic electrically charged particles, the beam is formed and imaged onto a target, where it generates a pattern image composed of pixels. The pattern image is moved along a path on the target over a region of exposure, and this movement defines a number of stripes covering said region in sequential exposures and having respective widths. The number of stripes are written parallel to each other along a general direction, which is at a small angle to a principal pattern direction of structures to be written within the region of exposure.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: September 10, 2019
    Assignee: IMS Nanofabrication GmbH
    Inventor: Elmar Platzgummer
  • Patent number: 10409939
    Abstract: A method including evaluating a configuration of a device for a selected device parameter and determining a value of the selected device parameter in a first optimal configuration that improves a performance of the device is provided. The method includes determining a sensitivity of the performance of the device relative to the value of the selected device parameter and determining a performance metric that differentiates the first optimal configuration with a second optimal configuration based on the sensitivity of the performance of the device. The method includes ranking the first optimal configuration and the second optimal configuration based on the performance metric and simulating the performance of the device with a second device parameter in one of the first optimal configuration or the second optimal configuration, based on the ranking. A system and a computer readable medium to perform the above method are also provided.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: September 10, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Michele Petracca, Yosinori Watanabe
  • Patent number: 10399447
    Abstract: A control method for a swappable battery pack set of electric vehicles (EVs), wherein each of the EVs has a main battery pack set and at least a swappable battery pack set simultaneously. The control method includes the following process of uninstalling the swappable battery pack set from a first EV, before charging the swappable battery pack set; executing a charge unlocking process, before charging the swappable battery pack set; executing a charge locking process, after charging the swappable battery pack set; and installing the swappable battery pack set to a second EV after executing the charge locking process.
    Type: Grant
    Filed: January 8, 2016
    Date of Patent: September 3, 2019
    Inventor: Chih-Chan Ger
  • Patent number: 10401737
    Abstract: A technique and method for determining a process dose for a beam lithography process includes accessing a data set that enables associating (i) a plurality of measured dimensions of features exposed by beam lithography with (ii) a plurality of different exposure doses, wherein the features were exposed with the different exposure doses, and with (iii) at least one of a plurality of different densities of the exposed features and a plurality of different nominal dimensions of the exposed features. The method also includes providing a model that is parameterized in at least the following parameters (i) measured feature dimension; (ii) exposure dose; (iii) at least one of feature density and nominal feature dimension; (iv) process dose; and (v) at least one process bias. In a further step, the method includes fitting the model with the data set to determine the process dose and the process bias.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: September 3, 2019
    Assignee: GenISys GmbH
    Inventors: Ulrich Hofmann, Nezih Uenal
  • Patent number: 10399452
    Abstract: A hybrid electric vehicle having one or more controllers, voltage-current sensors, and batteries, which are configured to generate and respond to power signals that communicate vehicle operating and start-up conditions, among other parameters and data. The components also are enabled to detect vehicle and battery conditions that include an open circuit voltage (OCV), current, differentiated current (DFC), and near zero current (NZC). The controller(s) are further configured to generate a predicted battery state of charge (SoC) from a combination of the OCV, current, DFC, NZC, and other parameters, which are calibrated according to respective magnitudes and noise calibration factors, which enables the controller(s) to charge and discharge the battery according to the predicted SoC.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: September 3, 2019
    Assignee: Ford Global Technologies, LLC
    Inventor: Xu Wang
  • Patent number: 10402533
    Abstract: Systems, methods, media, and other such embodiments are described for placement of cells in a multi-level routing tree, where placement of a mid-level parent node between a grandparent node and a set of child nodes is not set. One embodiment involves generating a first routing subregion between a first set of child nodes associated with a first grandparent node and a first connecting route from the first routing subregion to the first grandparent node, which together are set as a first routing region comprising the first routing subregion and the first connecting route. Sampling points are selected along the first routing region, and for each sampling point a set of operating values associated with the sampling point is calculated. A position for the parent node is selected based on the operating values for the sampling points.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: September 3, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: William Robert Reece, Yi-Xiao Ding, Thomas Andrew Newton, Charles Jay Alpert, Zhuo Li
  • Patent number: 10395001
    Abstract: A computer implemented method for decomposing a layout of a portion of an integrated circuit is presented. The layout includes a first multitude of polygons. The method includes constructing, using the computer, a first matrix representative of a first multitude of constraints. Each of the first multitude of constraints is between a different pair of the first multitude of polygons. The method includes solving, using the computer, the first matrix to thereby assign one of a multitude of masks to each different one of the first multitude of polygons, when the computer is invoked to decompose the layout.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: August 27, 2019
    Assignee: SYNOPSYS, INC.
    Inventor: Hua-Yu Chang