Patents Examined by Vuthe Siek
  • Patent number: 11150306
    Abstract: A state of charge estimation device includes a memory section, a measurement section, a time measurement section, and an estimation section. The memory section memorizes a specified dark current, which flows at an auxiliary battery while the vehicle is parked, and a first state of charge at a most recent time the vehicle was parked before being started. The measurement section measures an open circuit voltage. The time measurement section measures an elapsed time from the time the vehicle was parked to the time it is started. The estimation section updates the specified dark current memorized in the memory section such that a second state of charge approaches a third state of charge. If the open circuit voltage is in a first region, the estimation section estimates a state of charge on the basis of the first state of charge, the specified dark current, and an elapsed time.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: October 19, 2021
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Takayuki Akaishi
  • Patent number: 11146075
    Abstract: One exemplary embodiment provides a charging and discharging control apparatus for an energy storage apparatus, the charging and discharging control apparatus including: a charging and discharging controlling unit configured to control a charging and discharging current amount of the energy storage apparatus according to a droop curve; a communication unit configured to receive state information from the energy storage apparatus; and a droop curve adjusting unit configured to adjust a characteristic value of the droop curve according to the state information.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: October 12, 2021
    Assignee: KOREA INSTITUTE OF ENERGY RESEARCH
    Inventors: Su Yong Chae, Sea Seung Oh, Hak Geun Jeong, Jong Bok Baek, Soo Bin Han, Suk In Park
  • Patent number: 11137810
    Abstract: A charger comprises an input circuit that receives power from a power source, a converter circuit, an output circuit, and a switching circuit. The converter circuit is connected between the input circuit and a signal ground of the charger and converts the power from a first voltage to a second voltage. The signal ground is connected to a chassis ground of the charger. The output circuit is connected between an output of the converter circuit and the signal ground and the chassis ground, and outputs the second voltage to an output connector of the charger. The switching circuit is connected between the output of the input circuit and an electrically conducting casing of the output connector, and controls the converter circuit. The switching circuit and the electrically conducting casing of the output connector are not connected to the signal ground and the chassis ground of the charger.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: October 5, 2021
    Assignee: La-Z-Boy Incorporated
    Inventors: Tahir Ahmad, Jaime McPherson
  • Patent number: 11135938
    Abstract: According to one aspect, energy management or battery pack distribution may be achieved by receiving a location associated with a portable battery dispensing vehicle which carries or stocks modular battery replacement packs for electric vehicles, determining a location of a mobile device associated with the system for energy management, displaying the location associated with the portable battery dispensing vehicle and the location associated with the mobile device, receiving a request associated with a purchase of one of the modular battery replacement packs carried by the portable battery dispensing vehicle, and generating an instruction to credit an associated account with a virtual energy credit based on the request associated with the purchase of one or more of the modular battery replacement packs.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: October 5, 2021
    Assignee: HONDA MOTOR CO., LTD.
    Inventors: Takero Arima, James Marion Cournyer, Robert Uyeki, Geoffrey Woo Honda
  • Patent number: 11132207
    Abstract: Various techniques are provided to implement fast boot for programmable logic devices (PLDs). In one example, a method includes receiving configuration data associated with a PLD. The PLD includes an array of configuration memory cells including logic block memory cells and input/output (I/O) block memory cells associated with the PLD's logic fabric and I/O fabric, respectively. The method further includes programming a subset of the I/O block memory cells with the configuration data, and providing a wakeup signal to activate functionality associated with a portion of the I/O fabric. The method further includes programming remaining configuration memory cells of the array with the configuration data, where the remaining configuration memory cells include at least a subset of the logic block memory cells. The method further includes providing a wakeup signal to activate functionality associated with at least a portion of the logic fabric. Related systems and devices are provided.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: September 28, 2021
    Assignee: LATTICE SEMICONDUCTOR CORPORATION
    Inventors: Fulong Zhang, Gordon Hands, Satwant Singh, Wei Han, Ravindar Lail, Joel Copien, Sreepada Hegade, Ming Hui Ding
  • Patent number: 11133697
    Abstract: The wireless portable electronic charger recharges each of the one or more personal data devices. The wireless portable electronic charger: a) draws AC electrical energy from a national electric grid; and, b) wirelessly broadcasts the received AC electrical energy to the one or more personal data devices. The wireless portable electronic charger comprises an energy broadcast circuit and one or more induction circuits. The energy broadcast circuit broadcasts the received AC electrical energy to the one or more induction circuits. Each induction circuit selected from the one or more induction circuits: a) receives the AC electrical energy broadcast from the energy broadcast circuit; b) converts the received AC electrical energy into DC electrical energy suitable for use by a personal data device associated with the selected induction circuit; and, c) transmits the DC electrical energy to the battery of the personal data device.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: September 28, 2021
    Inventor: Emmanuel Ajayi
  • Patent number: 11132490
    Abstract: Various embodiments provide for clock network generation for a circuit design using a negative-edge integrated clock gate (ICG). According to some embodiments, a clock network with one or more negative-edge ICGs is generated, after a topology of the clock network is defined, by applying a positive-edge ICG-to-negative-edge ICG transform to one or more nodes of the clock network that comprise a positive-edge ICG. Additionally, according to some embodiments, a clock network is generated bottom-up (from the clock sinks to the root clock signal source) using one or more negative-edge ICGs.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: September 28, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Ruth Patricia Jackson, William Robert Reece, Thomas Andrew Newton, Zhuo Li
  • Patent number: 11119401
    Abstract: A method and an apparatus for determining near field images for optical lithography include receiving a thin mask image indicative of a photomask feature, in which the thin mask image is determined without considering a mask topography effect associated with the photomask feature, and determining a near field image from the thin mask image by a processor using an artificial neural network (ANN), in which the ANN uses data of the thin mask image as input. The apparatus includes a processor and a memory coupled to the processor. The memory is configured to store instructions executed by the processor to perform the method.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: September 14, 2021
    Assignee: ASML US, LLC
    Inventors: Jiangwei Li, Yumin Wang, Jun Liu
  • Patent number: 11114376
    Abstract: A system (including a processor and memory with computer program code) that is configured to execute a method which includes generating the layout diagram including: selecting a circuit cell which includes an active element; bundling, for purposes of placement, the circuit cell and an inter-layer via together as an integral unit; placing the integral unit of the circuit cell and the inter-layer via in a first device layer of the layout diagram; and placing a metal pattern in a second device layer of the layout diagram; and wherein the placing the integral unit of the circuit cell and the inter-layer via forms a direct electrical connection channel between the circuit cell and the metal pattern.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: September 7, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Lin Chuang, Ching-Fang Chen, Jia-Jye Shen
  • Patent number: 11113446
    Abstract: A computer system improves a production yield of a semiconductor chip described by design data. The computer system includes a synthesis controller in signal communication with a yield optimization controller. The synthesis controller generates design data representing a design implementation of the semiconductor chip. The yield optimization controller extracts timing information from the design data. The timing information describes a slack related to a timing path within the semiconductor chip. The yield optimization controller further identifies one or more one yield improvable cells described by the design data, and determines from the design data an adverse impact of yield improvement on the slack. Based on the timing information and the determined adverse impact, the yield optimization controller calculates a subset of the yield improvable cell, and modifies the subset of the yield improvable cell so that the production yield is improved.
    Type: Grant
    Filed: January 20, 2020
    Date of Patent: September 7, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas Makowski, Matthias Ringe, Andreas H. A. Arp, Michael V. Koch, Fatih Cilek
  • Patent number: 11106835
    Abstract: A method of manufacturing conductive lines in a circuit is disclosed. The method includes grouping signal traces into a first set of signal traces and a second set of signal traces, fabricating, using a first mask, at least a first conductive line of a first signal trace of the first set of signal traces, and fabricating, using a second mask, at least a second conductive line of a second signal trace of the second set of signal traces. Each signal trace of the first set of signal traces has a first width. Each signal trace of the second set of signal traces has a second width different from the first width. The grouping is based on at least a current of at least a signal trace of the signal traces.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: August 31, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Chung-Hui Chen
  • Patent number: 11108245
    Abstract: Disclosed herein is an electric battery charger system and method which may be used with electrical equipment such as an electric vehicle to improve the efficiency of operation. The charger system includes a DC motor operated by a car battery or other power source and a generator (e.g., turbine generator) to power a traction battery of the electric vehicle for recharging. In one embodiment, the charger system may have a single shaft running between the motor and generator with blades on the shaft to cool the operation of the charger system. In another embodiment, a coupler assembly is located between the motor and generator to drive the shaft of the generator. In another embodiment, the charger system may include fans having interlocking, non-contact blades which are kept apart by magnets located on the blades. A first fan is turned by the DC motor and is configured to drive a second fan which turns a shaft of the generator to create power for charging the traction battery.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: August 31, 2021
    Inventor: Benjamin Lujan
  • Patent number: 11101737
    Abstract: An on-board charging/discharging system includes a bidirectional converter and a low-voltage converter. When the high-voltage battery is charged or discharged by the bidirectional converter, the bidirectional converter is operated in a variable-frequency mode and the low-voltage converter is also operated in the variable-frequency mode. The on/off states of different switches are controlled according to the output gain of the bidirectional converter, and thus the on-board charging/discharging system has optimized volume and reduced cost. Moreover, the soft switching is achieved when the output gain is lower than 1, greater than 1 or equal to 1. Consequently, the efficiency of the on-board charging/discharging system is enhanced. Moreover, while the low-voltage converter is operated in a fixed-frequency mode, the first bridge of the bidirectional converter is correspondingly controlled. Consequently, the voltage of the bus capacitor is within a reasonable range.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: August 24, 2021
    Assignee: DELTA ELECTRONICS (SHANGHAI) CO., LTD.
    Inventors: Hao Sun, Minli Jia, Jinfa Zhang
  • Patent number: 11101669
    Abstract: A method for determining a state of health of a rechargeable battery includes: determining a change in charge within an upper border and a lower border of a charging state window, the change in charge being determined by summing up current values measured within the charging state window; determining an actual state of health by scaling the change in charge with the width of the charging state window and dividing by an initial charging capacity of the battery; and determining an average state of health by calculating a sliding average of the actual state of health with at least one previous determined state of health.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: August 24, 2021
    Assignee: ABB Schweiz AG
    Inventors: Timothy Patey, Reto Flueckiger, Oleksandr Sologubenko, Andreas Zgraggen
  • Patent number: 11093683
    Abstract: Systems and methods are provided for generating test patterns. In various embodiments, systems and methods are provided in which machine learning is utilized to generate the test patterns in a manner so that the test patterns conform with design rule check (DRC) specified for a particular semiconductor manufacturing process or for particular types of devices. A test pattern generation system includes test pattern generation circuitry which receives a noise image. The test pattern generation generates a pattern image based on the noise image, and further generates a test pattern based on the pattern image. The test pattern is representative of geometric shapes of an electronic device design layout that is free of design rule check violations.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: August 17, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fu-An Tien, Hsu-Ting Huang, Ru-Gun Liu
  • Patent number: 11087064
    Abstract: The present disclosure relates to a method for use with an electronic design. Embodiments may include receiving, using a processor, the electronic design and estimating a wire width associated with the electronic design based upon, at least in part, a current in a wire, a layer of the wire, a temperature, and an electromigration length. Embodiments may further include allowing, at a graphical user interface, a user to make an edit to a shape or a layer of the wire and generating a revised EM length, based upon, at least in part, the edit. Embodiments may also include generating one or more EM length breakpoints based upon, at least in part, the revised EM length and one or more EM rules.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: August 10, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Laurent René Saint-Marcel, Olivier Berger
  • Patent number: 11087033
    Abstract: A computing system generates a subset of design cases of candidate design cases. The system indexes, in the subset, data elements. The system generates a design of an experiment by, for each respective data element, determining a status indicating whether the respective data element corresponds to an uncontrolled factor or a controlled factor. When the status indicates the uncontrolled factor, the system determines if substituting a respective set of specified options of a respective candidate design case comprising the respective data element with a different set of specified options of the candidate design cases improves a criterion measure according to a design criterion. When the status indicates the controlled factor, the system determines if changing an assigned option of the respective data element improves the criterion measure. The system updates the criterion measure with an updated criterion measure according to a change of the subset based on generating the design.
    Type: Grant
    Filed: January 20, 2021
    Date of Patent: August 10, 2021
    Assignee: SAS Institute Inc.
    Inventors: Ryan Adam Lekivetz, Bradley Allen Jones, Joseph Albert Morgan, Caleb Bridges King
  • Patent number: 11087058
    Abstract: Embodiments of systems and methods for an FIB-aware anti-probing physical design flow are described in the present disclosure. Such embodiments incorporate new and improved security-critical steps in a physical design flow, in which the design is constrained to provide coverage on asset nets through an internal shield.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: August 10, 2021
    Assignee: University of Florida Research Foundation, Inc.
    Inventors: Domenic J. Forte, Mark M. Tehranipoor, Qihang Shi, Huanyu Wang, Haoting Shen
  • Patent number: 11087038
    Abstract: The present invention relates to the importance-directed geometric simplification of complex mesh-based representations of objects in virtual environments for radiosity-based global illumination simulations. By means of simplification, the time needed to solve the radiosity equation and so generate an accurate physically-based simulation can be markedly reduced. Further, geometric simplification is performed during the global illumination simulation process rather than as a preprocess step.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: August 10, 2021
    Inventors: Ian Edward Ashdown, Jasen Wright, Jack Thomas
  • Patent number: 11080444
    Abstract: Devices, methods, computer-readable media, and other embodiments are described for concurrent functional and fault co-simulation of a circuit design. One embodiment involves accessing simulation data for a circuit design made up of a plurality of machine regions. A plurality of faults is selected from the simulation data for co-simulation operations of functional simulation and fault simulation of the circuit design, and functional simulation of the plurality of machine regions is initiated using the simulation data. A first machine region is identified during the functional simulation as associated with at least a first fault of the plurality of faults. A functional simulation of the first machine region is performed, and a divergence point associated with the first fault is identified. A fault simulation for the first fault is performed using the functional simulation of the first machine region and the divergence point.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: August 3, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Manoj Kumar, David J. Roberts, Apurva Kalia