Patents Examined by Vuthe Siek
  • Patent number: 10810340
    Abstract: At the boundary where the number of effective chips changes, at least three grid points of a chip grid intersect with the periphery of a wafer effective region, and a triangle connecting these three grid points together includes therein the wafer center. To design a semiconductor chip, this feature is used to determine, by an analytic process, candidate solutions including different numbers of effective chips. These candidate solutions are used to derive an advantageous solution.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: October 20, 2020
    Assignee: LLC SUUGAKUYA HONPO
    Inventor: Youzou Fukagawa
  • Patent number: 10810347
    Abstract: The present disclosure provides a PCBA detection method and a system based on 3D AOI and AXI. The method includes: preconfiguring graphical data in a part physical database; obtaining CAD data related to a PCB based on design data input from PCB design software; converting the generated CAD data, and generating 3D basic graphical data to generate a 3D physical model; extracting BOM information from the design data, searching the part physical database for matched graphical data based on the BOM information, if the matched graphical data is found, generating a 3D physical model based on the graphical data; if the matched graphical data is not found, generating corresponding image data based on obtained created data, to generate a 3D physical model; and generating standard 3D detection prototype data, outputting the standard 3D detection prototype data to 3D AOI and AXI for detection.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: October 20, 2020
    Inventors: Shengjie Qian, Fengshou Liu, Pan Su, Zhongliang Zhu
  • Patent number: 10811890
    Abstract: An adapter and method for using a grasp-socket component with a handheld electronic device, the adapter including a base layer having a top and a bottom side, wherein the bottom side of the base layer connects to the handheld electronic device; and a top layer that includes a planar surface and a plurality of side walls, wherein the top layer is coupled to the base layer to form a partially-enclosed hollow space between the top side of the base layer and the planar surface of the top layer, wherein the top layer includes an elongated opening in the planar surface that is sized and shaped such that the grasp-socket component can be coupled to the top layer and such that the grasp-socket component can be moved to a plurality of positions along the top surface of the base layer by sliding the grasp-socket component within the partially-enclosed hollow space.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: October 20, 2020
    Inventor: Dustin J. Vail
  • Patent number: 10796041
    Abstract: Systems, methods, media, and other such embodiments described herein relate to improved operation of test devices which verify circuit operations. One embodiment involves accessing a circuit design comprising a plurality of instances of one or more blocks, where each block of the one or more blocks is associated with a corresponding block test pattern comprising one or more test subpatterns. Each corresponding block test pattern is processed to identify independent test subpatterns, and then each instance is processed to identify each independent test subpattern for the circuit design. Similar types of independent test subpatterns are merged into a circuit design test pattern, such that at least two of the independent test subpatterns associated with the circuit design occupy shared test cycles within the circuit design test pattern.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: October 6, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Rajesh Khurana, Vivek Chickermane, Divyank Mittal, Balveer Singh Koranga
  • Patent number: 10796042
    Abstract: Various embodiments provide for partial selection-based (e.g., cut-based) model extraction from a layout of a circuit design, which can be used to generate a schematic extracted view for the circuit design and to back annotate a schematic of the circuit design. For some embodiments, the selection comprises a cut of a layout of a circuit design, where the cut may be defined (e.g., inputted) by a user through a graphical user interface that is presenting the layout.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: October 6, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventor: Balvinder Singh
  • Patent number: 10782354
    Abstract: A low voltage threshold adjusting method is provided and includes the following steps: detecting whether a present voltage is lower than a low voltage threshold; detecting whether a present current exceeds a preset current threshold in response to that the present voltage is lower than the low voltage threshold; detecting whether a present temperature exceeds a preset temperature in response to that the present current exceeds the preset current threshold; checking whether a current state of charge (SOC) is higher than a preset SOC in response to that the present temperature does not exceed the preset temperature; and decreasing the low voltage threshold in response to that the current SOC is higher than the preset SOC.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: September 22, 2020
    Assignee: Acer Incorporated
    Inventor: Chu-Hsiang Hsu
  • Patent number: 10769341
    Abstract: A simulated-evolution-based macro refinement method includes evaluating a score of each placed macro cell to be refined; generating a random number; determining whether the score satisfies a predetermined condition; placing the macro cell into a queue if the score associated with the macro cell satisfies the predetermined condition; and sorting and placing macro cells of the queue according to scores of the macro cells in the queue.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: September 8, 2020
    Assignees: NCKU Research and Development Foundation, Himax Technologies Limited
    Inventors: Chia-Min Lin, You-Lun Deng
  • Patent number: 10769335
    Abstract: An electronic design automation (EDA) tool for executing topological and functional checks on an electronic circuit design (ECD) includes a processor and a memory that stores the ECD, graphical rules, and filter rules for executing the checks. The processor generates a test graph based on the ECD, replaces stretchable nodes with nested networks in the test graph to generate extended graphs, and decouples real edges and functional edges of each extended graph to generate real graphs and functional graphs, respectively. Based on the graphical rules, the processor executes the topological checks on an input graph of the ECD to identify real sub-graphs from the input graph that are isomorphic to a real graph. The processor further generates functional sub-graphs by combining a functional graph with each real sub-graph, and based on the filter rules, further executes the functional checks on the functional sub-graphs to identify output graphs.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: September 8, 2020
    Assignee: NXP USA, Inc.
    Inventors: Pushkar Sareen, Abinash, Piyush Pandey
  • Patent number: 10769333
    Abstract: The present disclosure relates to a method for electronic design verification. Embodiments may include providing, using a processor, an electronic design and determining one or more design violations based upon, at least in part, a structural observability filter. Embodiments may also include generating a violation trace based upon, at least in part, the one or more design violations and displaying the violation trace at a graphical user interface configured to allow a user to debug the one or more design violations. Embodiments may further include allowing the user to select at least one path to be waived at the graphical user interface and generating a new violation trace without the at least one path to be waived.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: September 8, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Maayan Ziv, Nizar Hanna, Sanaa Halloun
  • Patent number: 10762272
    Abstract: The present disclosure provides a pattern density analysis method for analyzing a local pattern density of a layout, the method comprising: obtaining a pattern attribute of each layout pattern located on a layout region to be analyzed; setting, for each layout pattern, a relevant window for the layout pattern based on the corresponding pattern attribute; calculating the pattern density of each relevant window; and selecting the maximum value of the pattern densities of the relevant windows as the maximum local pattern density of the layout, and selecting the minimum value of the pattern densities of the relevant windows as the minimum local pattern density of the layout.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: September 1, 2020
    Inventors: Wei Cheng, Zhonghua Zhu, Fang Wei
  • Patent number: 10759293
    Abstract: A galvanic isolation in the power electronics system of an electricity charging station having the following features: a rectifier (11) for connection of the charging station (10) to a public low-voltage network and a galvanically isolating DC voltage converter (12) having a high clock frequency and connected to the rectifier (11) and a corresponding electricity charging station.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: September 1, 2020
    Assignees: Dr. Ing. h.c. F. Porsche Aktiengesellschaft, ads-tec GmbH
    Inventors: Raoul Heyne, Florian Joslowski, Michael Kiefer, Thomas Speidel, Ali Natour
  • Patent number: 10763554
    Abstract: A deteriorated capacity calculator calculates a deteriorated capacity that is a capacity reduced from the capacity of a cell in an initial state. A gas amount calculator calculates an amount of gas contained in a container for the cell, from the deteriorated capacity. A pressure calculator calculates a pressure inside the container for the cell from the amount of the gas, a volume of a void space of the container for the cell and the temperature of the cell. A pressure monitor outputs a control signal for stopping charging or discharging of the battery when the pressure inside the container for at least any one cell is equal to or greater than a threshold pressure.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: September 1, 2020
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yukihiro Yoshida, Sho Shiraga, Satoshi Hara, Yuruki Okada
  • Patent number: 10762260
    Abstract: Disclosed are methods, systems, and articles of manufacture for implementing an electronic design having embedded circuits. These techniques identify a specification of an electronic design, a parameter for optimization, at least one optimization target for the parameter, and initial grids for the electronic design. An optimization map may be determined, by at one or more optimization modules that are stored at least partially in memory of and function in conjunction with at least one microprocessor of a computing system, for the electronic design at least by performing one or more analyses that refine the initial grids for the optimization map with respect to the parameter and the at least one optimization target. The electronic design may be implemented based at least in part upon the optimization map.
    Type: Grant
    Filed: September 30, 2018
    Date of Patent: September 1, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Jian Liu, Jing Wang, Chun-Teh Kao, An-Yu Kuo
  • Patent number: 10763707
    Abstract: A control method of a wireless power transmitter and a wireless power transmitter. The method includes transmitting a first power with a first cycle; transmitting a second power with a second cycle, wherein the second cycle is greater than the first cycle; when a wireless power receiver is placed within a charging area and is detected by the first power, upon detecting the wireless power receiver by the first power, transmitting a third power to drive the wireless power receiver to transmit a search signal to the wireless power transmitter; and when the wireless power receiver is placed within the charging area and is not detected by the first power, using the second power to detect the wireless power receiver and drive the wireless power receiver to transmit the search signal to the wireless power transmitter.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: September 1, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung-Woo Lee, Kang-Ho Byun, Hee-Won Jung
  • Patent number: 10755024
    Abstract: The present disclosure relates to a system and method for routing in an electronic circuit design. Embodiments may include providing, using a processor, a hierarchical electronic design having a plurality of partitions, at least one routing blockage, a source pin location, and one or more sink pin locations. Embodiments may also include generating a routing wire network configured to connect the source pin location and the one or more sink pin locations to create one or more segments, wherein generating the routing wire network includes creating two or more feed-through ports at one or more of the plurality of partitions. Embodiments may further include applying a maze-routing approach to each of the one or more segments of the routing wire network to form a routed net associated with the hierarchical electronic design.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: August 25, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Wing Kai Chow, Mehmet Yildiz, Zhuo Li
  • Patent number: 10740528
    Abstract: A method of generating, by a computing device, a 3D circuit layout based on a 2D circuit layout, the method comprising: assigning cells of first and second groups of circuit cells of the 2D circuit layout to first and second levels of the 3D circuit layout, the assignment of each circuit cell of the first and second groups being performed by: selecting, among at least one first row of a first level of the 3D circuit layout and at least one second row of a second level of the 3D circuit layout, the row having the greatest available space; and assigning the circuit cell to the selected row; and transmitting the 3D circuit layout to a manufacturing plant for fabrication.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: August 11, 2020
    Assignee: Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventors: Guillaume Berhault, Olivier Billoint, Sébastien Thuries
  • Patent number: 10740524
    Abstract: A decoder is implemented in a field programmable gate array (FPGA) by performing logic simplification of binary expressions associated with the decoder. To perform the logic simplification, the binary expressions are arranged in a binary matrix. Further, a set of submatrices is formed based on the binary expressions such that rows of each submatrix have common data bits in one or more columns of each submatrix. Based on the common data bits, a set of subexpressions for each submatrix is formed. The set of subexpressions of each submatrix is mapped into look-up table clusters of the FPGA, thereby implementing the decoder in the FPGA.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: August 11, 2020
    Inventor: Shriharsha Koila
  • Patent number: 10733343
    Abstract: The invention is suited for use by a hardware designer for the purpose of logic synthesis and/or logic simulation. It can be used in the design of integrated circuits (ASICs) and programmable logic devices (PLDs), such as field-programmable gate arrays (FPGAs). The invention also relates to the field of hardware description languages (HDLs). Embodiments of the invention provide a computer-implemented system and method for facilitating the design of a digital circuit which comprises a plurality of logical constructs. The system is configured such that each time each logical construct is executed during a software simulation pass it is associated with a unique tag, wherein each tag can correspond to a physical aspect of a hardware representation of the design. The simulation is performed by repeated execution passes through code which implements the design, preferably wherein the same tags are associated with corresponding executions of the logical constructs during different simulation passes.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: August 4, 2020
    Assignee: LAMBDA LOGIC LIMITED
    Inventor: Graham Clemow
  • Patent number: 10726878
    Abstract: A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: July 28, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takafumi Betsui, Naoto Taoka, Motoo Suwa, Shigezumi Matsui, Norihiko Sugita, Yoshiharu Fukushima
  • Patent number: 10714958
    Abstract: The invention provides a charging apparatus and an operating method thereof. The charging apparatus includes a power conversion circuit, a feedback circuit, an identifier control circuit, and a low voltage trickle control circuit. The feedback circuit generates a feedback signal for the power conversion circuit, and the power conversion circuit correspondingly adjusts a charging power according to the feedback signal. The power conversion circuit provides the charging power to charge a battery device. The identifier control circuit determines whether to control the feedback circuit to change the feedback signal according to identifier information of the battery device. The low voltage trickle control circuit determines whether to control the feedback circuit to change the feedback signal according to a voltage of the charging power. When the low voltage trickle control circuit controls the feedback circuit to change the feedback signal, the feedback circuit ignores control of the identifier control circuit.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: July 14, 2020
    Assignee: Chicony Power Technology Co., Ltd.
    Inventors: Shuo-Kuo Huang, Yuan-Jing Liu