Abstract: Efficient synthesis of arbitrary quantum states and unitaries from a universal fault tolerant gate-set (e.g., Clifford+T) is a goal in quantum computation. As physical quantum computers are fixed in size, all available qubits should be used if it minimizes overall gate counts, especially that of the expensive T-gates. In this application, a quantum algorithm is described for preparing any dimension-N quantum state specified by a list of N classical numbers, that realizes a trade-off between space and T-gates. Example embodiments exploit (?) ancilla qubits, to reduce the T-gate cost to ???? ? ( N ? + ?log 2 ? N ? ) . Notably, this it proven to be optimal up to logarithmic factors for any ?=o(?{square root over (N)}) through an unconditional gate counting argument. Though (N) Clifford gates are always required, only (?{square root over (N)}) T-gates are needed in the best case, which is a quadratic improvement over prior art.

Abstract: A method for providing, based on an emulation schedule, a reset message to multiple circuits is provided. The reset message associates a reset signal with a selected clock cycle for each circuit, in the emulation schedule. The method includes determining a mask for each of the circuits based on the emulation schedule, providing a clock signal to the circuits, the clock signal comprising the selected clock cycle for each circuit, and tuning the reset signal relative to the clock signal based on a center of the selected clock cycle for each circuit. The method also includes providing the reset signal to the circuits and asserting the reset signal in the circuits based on the mask. A system and a non-transitory, machine-readable medium storing instructions to perform the above method are also provided.

Abstract: A method for designing a system on a target device includes performing high-level compilation on a high-level language source file to generate a hardware description language (HDL) of the system and a serial testbench for the system. Verification is performed on the system that examines a parallel nature of the system by using the serial testbench.

Abstract: A method of manufacturing an apparatus and a method of constructing an integrated circuit are provided. The method of manufacturing an apparatus includes forming the apparatus on a wafer or a package with at least one other apparatus, wherein the apparatus comprises a polynomial generator, a first matrix generator, a second matrix generator, a third matrix generator, and a convolution generator; and testing the apparatus, wherein testing the apparatus comprises testing the apparatus using one or more electrical to optical converters, one or more optical splitters that split an optical signal into two or more optical signals, and one or more optical to electrical converters.

Abstract: A design tool can implement phase algebra based design evaluation to evaluate a circuit design with a compact representation of numerous waveforms without simulating the individual waveforms. The design tool can determine an input sequence of signal transition representations associated with an input net of a component in RTL circuit design, where each signal transition representation represents a nondeterministic transition from a previous signal state to possible signal state(s). Determining the input sequence of signal transition representations includes determining that the input sequence of signal transition representations indicates an input gated clock waveform. The design tool also can determine, based on the indicated component and on the input gated clock waveform, an output sequence of signal transition representations derived from the input sequence of signal transition.

Abstract: A control equipment and a control method of a stepper are provided. The control equipment of the stepper includes an input device, a generating device and a processing device. The input device is configured to input a plurality of sample development patterns. The sample development patterns are obtained according to a plurality of sample focal length values. The generating device is configured to generate a plurality of generative categories corresponding to a plurality of generative focal length values by using a depth learning algorithm. The processing device is configured to analyze an estimated focal length value of the online development pattern according to the generative categories.

Abstract: The present disclosure relates to a computer-implemented method for use in a formal verification of an electronic design. Embodiments may include receiving a reference model including a software specification, an implementation model at a register transfer level, and a property that analyzes equivalence between the reference model and the implementation model. The method may further include generating one or more case split hints based upon the reference model, that may be used to decompose the design state space into smaller partitions and performing an abstraction operation on a portion of design logic associated with one or more partitions in order to eliminate design elements that are irrelevant to a particular property. Embodiments may also include performing model checking on the abstract models to determine their accuracy.

Abstract: Disclosed approaches for creating a circuit design involving a network-on-chip (NoC) include instantiating in a memory of a computer system logic blocks and logical NoC (LNoC) blocks. Each logic block specifies a function of the circuit design and is communicatively coupled to another logic block through an LNoC block. The LNoC blocks are aggregated into a traffic specification that specifies connections between ingress circuits and egress circuits of the NoC. The traffic specification is compiled into configuration parameters for circuits of the NoC, and the logic blocks are compiled into implementation data for the target IC by the computer processor. The target IC can then be configured with the configuration parameters and implementation data.

Abstract: Systems and methods for a deterministic automatic test generation (ATPG) process including Timing Exception ATPG (TEA). A method includes performing an automated test pattern generation (ATPG) process that uses timing exception information to generate a test pattern for a targeted fault of a circuit design with at least one timing exception path. The method includes testing the targeted fault of the circuit design using the test pattern to produce a test result for the targeted fault.

Abstract: A semiconductor apparatus includes a substrate, a first die, and a second die. The substrate includes first and second byte pads of a first channel and first and second byte pad of a second channel. First byte pads of the first die are respectively coupled to the first byte pads of the first channel, and second byte pads of the first die are respectively coupled to the second byte pads of the first channel. The second die, as disposed, is rotated by 180° with respect to the first die. First byte pads of the second die are respectively coupled to the second byte pads of the second channel, and second byte pads of the second die are respectively coupled to the first byte pads of the second channel.

Abstract: An assembly for supporting and charging a dental device. The assembly has three major components comprising a charging base, a rinsing cup and a dental device. The assembly allows the charging base to wirelessly charge the dental device when the dental device is placed within the rinsing cup, which is located on top of the charging base. The bottom interior surface of the rinsing cup has a convex dome that helps stabilize the assembly. The dental device further includes a magnet to ensure stability and promote reliable charging.

Abstract: A method for adding an electrical interconnection within a three-dimensional integrated circuit (3-D IC) is disclosed. The method may include creating, within a design file of a 3-D IC that specifies a layout for a first chip of the 3-D IC, design data corresponding to a set of through-silicon via (TSV) reservation areas. The method may also include receiving an engineering change order (ECO) and releasing, in response to the ECO, at least one TSV reservation area for reuse. The method may also include adding, by re-using at least one TSV reservation area, an electrical interconnection within the design file of the first chip of the 3-D IC.

Abstract: A FIT evaluation method for an IC is provided. The FIT evaluation method includes accessing data representing a layout of the IC comprising a number of metal lines and a number of VIAs; picking a number of nodes along the metal lines; dividing each of the metal lines into a number of metal segments based on the nodes; and determining a FIT value for each of the metal segments or VIAs to verify the layout and fabricate the IC.

Abstract: The invention concerns a method of generating a digital signature of a geometric design represented by a geometric design file, the method involving generating, by a data processing device, the digital signature based on a single axis projection of the geometric design.

Abstract: In a general aspect, a quantum process for execution by a quantum processor is generated. In some instances, test data representing a test output of a quantum process are obtained. The test data are obtained based on a value assigned to a variable parameter of the quantum process. An objective function is evaluated based on the test data, and an updated value is assigned to the variable parameter based on the evaluation of the objective function. The quantum process is provided for execution by a quantum processor, and the quantum process provided for execution has the updated value assigned to the variable parameter.

Abstract: A method of making an integrated circuit includes operations to identify reverse signal nets of the circuit layout, determine when the conductive lines to the reverse signal net have parasitic capacitance, and determine how to adjust an integrated circuit layout to reduce the parasitic capacitance of the conductive lines to the reverse signal net. The method further includes an operation to determine whether to move one of the conductive lines in the integrated circuit layout, and an operation to determine whether to insert an isolation structure between the conductive lines of the reverse signal net having parasitic capacitance.

Abstract: A method includes assigning a default voltage value of a voltage domain in an integrated circuit (IC) schematic to a net in the voltage domain, generating a simulation voltage value of the net by performing a circuit simulation on the net, and modifying the IC schematic to include a voltage value associated with the net, based on the simulation voltage value of the net.

Abstract: Methods, systems and computer program products for improved metal fill shape removal from selected nets are provided. Aspects include determining a first set and second set of timing characteristics of a first and second circuit design, respectively. The first circuit design does not include metal fill shapes around a plurality of nets, whereas the second circuit design does include metal fill shapes around a plurality of nets. Aspects also include identifying a set of candidate nets based on a comparison of the first set of timing characteristics to the second set of timing characteristics. The set of candidate nets are nets that are candidates for metal fill shape removal. Aspects include generating a third circuit design by removing one or more metal fill shapes positioned around each net of the set of candidate nets that are positioned within a radius of removal.

Abstract: A method (of manufacturing a semiconductor device) includes, for a layout diagram stored on a non-transitory computer-readable medium, generating the layout diagram including: populating a row which extends in a first direction with a group of cells, each cell representing a circuit, and first and second side boundaries of each cell being substantially parallel and extending in a second direction which is substantially perpendicular to the first direction; locating, relative to the first direction, cells so that neighboring ones of the cells are substantially abutting; and reducing an aggregate leakage tendency of the group by performing at least one of the following, (A) changing an orientation of at least one of the cells, or (B) changing locations correspondingly of at least two of the cells.

Abstract: Various embodiments of the disclosure disclosed herein provide techniques for pre-silicon testing of a design for an integrated circuit. A pre-silicon testing system identifies one or more critical paths included in the integrated circuit. The pre-silicon testing system performs a based noise simulation to generate one or more voltage waveforms at each gate associated with the one or more critical paths. The pre-silicon testing system applies the one or more voltage waveforms to one or more netlists corresponding to the one or more critical paths to generate one or more modified netlists. The pre-silicon testing system performs a timing analysis on the one or more modified netlists to determine a set of slack times that correspond to a set of voltages applied to the integrated circuit. The pre-silicon testing system determines a first critical path that has a lowest slack time relative to all other critical paths.