Abstract: The wireless portable electronic charger recharges each of the one or more personal data devices. The wireless portable electronic charger: a) draws AC electrical energy from a national electric grid; and, b) wirelessly broadcasts the received AC electrical energy to the one or more personal data devices. The wireless portable electronic charger comprises an energy broadcast circuit and one or more induction circuits. The energy broadcast circuit broadcasts the received AC electrical energy to the one or more induction circuits. Each induction circuit selected from the one or more induction circuits: a) receives the AC electrical energy broadcast from the energy broadcast circuit; b) converts the received AC electrical energy into DC electrical energy suitable for use by a personal data device associated with the selected induction circuit; and, c) transmits the DC electrical energy to the battery of the personal data device.

Abstract: Various embodiments provide for clock network generation for a circuit design using a negative-edge integrated clock gate (ICG). According to some embodiments, a clock network with one or more negative-edge ICGs is generated, after a topology of the clock network is defined, by applying a positive-edge ICG-to-negative-edge ICG transform to one or more nodes of the clock network that comprise a positive-edge ICG. Additionally, according to some embodiments, a clock network is generated bottom-up (from the clock sinks to the root clock signal source) using one or more negative-edge ICGs.

Abstract: A method and an apparatus for determining near field images for optical lithography include receiving a thin mask image indicative of a photomask feature, in which the thin mask image is determined without considering a mask topography effect associated with the photomask feature, and determining a near field image from the thin mask image by a processor using an artificial neural network (ANN), in which the ANN uses data of the thin mask image as input. The apparatus includes a processor and a memory coupled to the processor. The memory is configured to store instructions executed by the processor to perform the method.

Abstract: A system (including a processor and memory with computer program code) that is configured to execute a method which includes generating the layout diagram including: selecting a circuit cell which includes an active element; bundling, for purposes of placement, the circuit cell and an inter-layer via together as an integral unit; placing the integral unit of the circuit cell and the inter-layer via in a first device layer of the layout diagram; and placing a metal pattern in a second device layer of the layout diagram; and wherein the placing the integral unit of the circuit cell and the inter-layer via forms a direct electrical connection channel between the circuit cell and the metal pattern.

Abstract: A computer system improves a production yield of a semiconductor chip described by design data. The computer system includes a synthesis controller in signal communication with a yield optimization controller. The synthesis controller generates design data representing a design implementation of the semiconductor chip. The yield optimization controller extracts timing information from the design data. The timing information describes a slack related to a timing path within the semiconductor chip. The yield optimization controller further identifies one or more one yield improvable cells described by the design data, and determines from the design data an adverse impact of yield improvement on the slack. Based on the timing information and the determined adverse impact, the yield optimization controller calculates a subset of the yield improvable cell, and modifies the subset of the yield improvable cell so that the production yield is improved.

Abstract: A method of manufacturing conductive lines in a circuit is disclosed. The method includes grouping signal traces into a first set of signal traces and a second set of signal traces, fabricating, using a first mask, at least a first conductive line of a first signal trace of the first set of signal traces, and fabricating, using a second mask, at least a second conductive line of a second signal trace of the second set of signal traces. Each signal trace of the first set of signal traces has a first width. Each signal trace of the second set of signal traces has a second width different from the first width. The grouping is based on at least a current of at least a signal trace of the signal traces.

Abstract: Disclosed herein is an electric battery charger system and method which may be used with electrical equipment such as an electric vehicle to improve the efficiency of operation. The charger system includes a DC motor operated by a car battery or other power source and a generator (e.g., turbine generator) to power a traction battery of the electric vehicle for recharging. In one embodiment, the charger system may have a single shaft running between the motor and generator with blades on the shaft to cool the operation of the charger system. In another embodiment, a coupler assembly is located between the motor and generator to drive the shaft of the generator. In another embodiment, the charger system may include fans having interlocking, non-contact blades which are kept apart by magnets located on the blades. A first fan is turned by the DC motor and is configured to drive a second fan which turns a shaft of the generator to create power for charging the traction battery.

Abstract: A method for determining a state of health of a rechargeable battery includes: determining a change in charge within an upper border and a lower border of a charging state window, the change in charge being determined by summing up current values measured within the charging state window; determining an actual state of health by scaling the change in charge with the width of the charging state window and dividing by an initial charging capacity of the battery; and determining an average state of health by calculating a sliding average of the actual state of health with at least one previous determined state of health.

Abstract: An on-board charging/discharging system includes a bidirectional converter and a low-voltage converter. When the high-voltage battery is charged or discharged by the bidirectional converter, the bidirectional converter is operated in a variable-frequency mode and the low-voltage converter is also operated in the variable-frequency mode. The on/off states of different switches are controlled according to the output gain of the bidirectional converter, and thus the on-board charging/discharging system has optimized volume and reduced cost. Moreover, the soft switching is achieved when the output gain is lower than 1, greater than 1 or equal to 1. Consequently, the efficiency of the on-board charging/discharging system is enhanced. Moreover, while the low-voltage converter is operated in a fixed-frequency mode, the first bridge of the bidirectional converter is correspondingly controlled. Consequently, the voltage of the bus capacitor is within a reasonable range.

Abstract: Systems and methods are provided for generating test patterns. In various embodiments, systems and methods are provided in which machine learning is utilized to generate the test patterns in a manner so that the test patterns conform with design rule check (DRC) specified for a particular semiconductor manufacturing process or for particular types of devices. A test pattern generation system includes test pattern generation circuitry which receives a noise image. The test pattern generation generates a pattern image based on the noise image, and further generates a test pattern based on the pattern image. The test pattern is representative of geometric shapes of an electronic device design layout that is free of design rule check violations.

Abstract: The present disclosure relates to a method for use with an electronic design. Embodiments may include receiving, using a processor, the electronic design and estimating a wire width associated with the electronic design based upon, at least in part, a current in a wire, a layer of the wire, a temperature, and an electromigration length. Embodiments may further include allowing, at a graphical user interface, a user to make an edit to a shape or a layer of the wire and generating a revised EM length, based upon, at least in part, the edit. Embodiments may also include generating one or more EM length breakpoints based upon, at least in part, the revised EM length and one or more EM rules.

Abstract: A computing system generates a subset of design cases of candidate design cases. The system indexes, in the subset, data elements. The system generates a design of an experiment by, for each respective data element, determining a status indicating whether the respective data element corresponds to an uncontrolled factor or a controlled factor. When the status indicates the uncontrolled factor, the system determines if substituting a respective set of specified options of a respective candidate design case comprising the respective data element with a different set of specified options of the candidate design cases improves a criterion measure according to a design criterion. When the status indicates the controlled factor, the system determines if changing an assigned option of the respective data element improves the criterion measure. The system updates the criterion measure with an updated criterion measure according to a change of the subset based on generating the design.

Abstract: The present invention relates to the importance-directed geometric simplification of complex mesh-based representations of objects in virtual environments for radiosity-based global illumination simulations. By means of simplification, the time needed to solve the radiosity equation and so generate an accurate physically-based simulation can be markedly reduced. Further, geometric simplification is performed during the global illumination simulation process rather than as a preprocess step.

Abstract: Embodiments of systems and methods for an FIB-aware anti-probing physical design flow are described in the present disclosure. Such embodiments incorporate new and improved security-critical steps in a physical design flow, in which the design is constrained to provide coverage on asset nets through an internal shield.

Abstract: Devices, methods, computer-readable media, and other embodiments are described for concurrent functional and fault co-simulation of a circuit design. One embodiment involves accessing simulation data for a circuit design made up of a plurality of machine regions. A plurality of faults is selected from the simulation data for co-simulation operations of functional simulation and fault simulation of the circuit design, and functional simulation of the plurality of machine regions is initiated using the simulation data. A first machine region is identified during the functional simulation as associated with at least a first fault of the plurality of faults. A functional simulation of the first machine region is performed, and a divergence point associated with the first fault is identified. A fault simulation for the first fault is performed using the functional simulation of the first machine region and the divergence point.

Abstract: According to one embodiment, a method, computer system, and computer program product for creating a plurality of process parameters in a circuit design is provided. The present embodiment of the invention may include receiving one parasitic extraction per layer of a circuit is used to obtain a resistance base factor and a capacitance base factor. The embodiment may further include performing Monte Carlo simulations to determine distributions of capacitance and resistance for each metal layer of the circuit, and creating scalars that scale each of the resistance base factor and the capacitance base factor to a minimum and maximum process limit. Additionally, the embodiment may include defining at least one delay corner using the created scalars, and receiving the results of one or more timing analyses performed using the resistance base factor and the capacitance base factor, and the defined delay corner to determine a delay variability per layer.

Abstract: A method of electrical device manufacturing that includes measuring a first plurality of dimensions and electrical performance from back end of the line (BEOL) structures; and comparing the first plurality of dimensions with a second plurality of dimensions from a process assumption model to determine dimension variations by machine vision image processing. The method further includes providing a plurality of scenarios for process modifications by applying machine image learning to the dimension variations and electrical variations in the in line electrical measurements from the process assumption model. The method further includes receiving production dimension measurements and electrical measurements at a manufacturing prediction actuator. The at least one of the dimensions or electrical measurements received match one of the plurality of scenarios the manufacturing prediction actuator using the plurality of scenarios for process modifications effectuates a process change.

Abstract: Systems and methods for optimizing data flow in an integrated circuit includes creating a task graph based on transforming an optimized network graph for a neural network application, wherein creating the task graph includes: enumerating a plurality of distinct tasks based on a decomposition of each of a plurality of network operations of the optimized network graph; and allocating a data buffer to each of pairs of dependent tasks of the plurality of distinct tasks based on the decomposition of each of the plurality of network operations of the optimized network graph; encoding a token-informed task scheduler based on a composition of the task graph, wherein the encoding the token-informed task scheduler includes: programming the token-informed task scheduler to cause an execution of the plurality of distinct tasks based on identifying a state of a respective data buffer between each of the pairs of dependent tasks.

Abstract: A simulation apparatus includes a memory and a processor. The processor is configured to: acquire a circuit model described in a hardware description language; extract a reading and writing relationship between a process and a register variable included in the circuit model; determine an evaluation order of the process, based on the number of register variables whose extracted relationship satisfies a given condition; and convert, into a blocking variable, a register variable which satisfies the given condition in the determined evaluation order of the process among the register variables included in the circuit model.

Abstract: An electric circuit switches connection among a plurality of storage cell units including a first storage cell unit and a second storage cell unit, a load of the plurality of storage cell units, and a power supply supplying power to the plurality of storage cell units.