Abstract: A method for compiling a quantum circuit on a trapped-ion quantum processor includes: obtaining a quantum circuit containing only a first predetermined category of two-qubit quantum gates, and/or one-qubit quantum gates; a step of compiling the quantum gates so that they only contain collective or entangling N-qubit quantum gates of a third predetermined category, one-qubit quantum gates of a fourth predetermined category, and so that all or at least some of those collective or entangling quantum gates simultaneously apply to at least three qubits, advantageously simultaneously apply to the majority of qubits, and even more advantageously simultaneously apply to all the qubits; and a step of grouping together the compiled quantum gates in a compiled quantum circuit.

Abstract: An apparatus for verification of a digital circuit includes a memory and a processor. The memory is configured to store a model of at least part of the digital circuit and a list of one or more locked-state tests, each locked-state test including a start state, an end state and a radius parameter. The processor is configured to formally prove that for at least one of the locked-state tests, a maximum distance between the start state and the end state is bounded by a number that is not greater than the radius parameter, thereby verifying that the start state is not a locked state.

Abstract: A battery system includes: a plurality of battery cells electrically connected to each other in series between a first node and a second node; an intermediate node dividing the plurality of battery cells into a first subset of battery cells and a second subset of battery cells; a step-down converter connected in parallel with the plurality of battery cells between the first node and the second node and having an output node; a first diode, an anode of which is connected to the intermediate node and a cathode of which is connected to the output node; and a control unit interconnected between the output node and the first node and configured to control the step-down converter.

Abstract: Some embodiments are directed to the design and manufacture of integrated circuits, and more particularly, some embodiments are directed to the electrical modeling of integrated circuits combining high voltage power devices with low voltage control logic blocks, and even more particularly, some embodiments are directed to the modeling of substrate coupling effects in these circuits.

Abstract: One or more processors determine a predicted sorting bin of a semiconductor device, based on measurement and test data performed on the semiconductor device subsequent to a current metallization layer. A current predicted sorting bin and a target soring bin are determined by a machine learning model for the semiconductor device; the target bin include higher performance semiconductor devices than the predicted sorting bin. The model determines a performance level improvement attainable by adjustments made to process parameters of subsequent metallization layers of the semiconductor device. Adjustments to process parameters are generated, based on measurement and test data of the current metallization layer of semiconductor device, and the adjustment outputs for the process parameters of the subsequent metallization layers of the semiconductor device are made available to the one or more subsequent metallization layer processes by a feed-forward mechanism.

Abstract: A charge/discharge switch control circuit for a battery pack includes a set of driving terminals and detection circuitry coupled to the driving terminals. The driving terminals provide driving signals to control a status of a switch circuit to enable charging or discharging of the battery pack. The detection circuitry receives voltages at multiple terminals of the switch circuit, and detects a status of an interface of the battery pack according to the status of the switch circuit and a difference between the voltages. The interface can receive power to charge the battery pack and provide power from the battery pack to a load.

Abstract: An electronic device earned around by the user is desired to be used for a long period. In order to achieve this, a high-capacity battery may be incorporated. Since a high-capacity battery is large, its incorporation in an electronic device increases the weight of the electronic device. An electronic device used while being implanted in the body of the user, provided with an emergency power supply, is provided, in an electronic device provided with a plurality of batteries, a transmitting portion and a receiving portion conduct wireless charging among different batteries, and the battery to be charged or used is selected by a power supply management circuit depending on the circumstances.

Abstract: A method for developing a method for compiling a quantum circuit on a quantum processor, comprising: a selection step: of a quantum circuit, of a quantum processor whereupon to compile the quantum circuit, of a set of quantum gates that can be executed on the selected quantum processor, of a metric, a meta-heuristic, a step of division of the selected quantum circuit into quantum sub-circuits, a first step of re-writing of the quantum sub-circuits comprising quantum gates that cannot be executed by the selected quantum processor to comprise only quantum gates that can be executed by the selected quantum processor, a second step of re-writing of the quantum sub-circuits, by the selected meta-heuristic, to obtain quantum sub-circuits comprising quantum gates that can be executed by the selected quantum processor, improving the selected metric, a step of regrouping of the quantum sub-circuits in a quantum circuit compilable by the selected quantum processor.

Abstract: Provided is a ternary logic synthesis method at least temporarily performed by a computer, the ternary logic synthesis method including generating a switching table with respect to pull-up and pull-down circuits using a truth table corresponding to a ternary function, converting the switching table into a sum of products (SOP) using a Quine-McCluskey algorithm, minimizing the SOP, and mapping a transistor corresponding to the SOP.

Abstract: A method includes accessing, from a memory, a schematic diagram of a circuit that depicts components of the circuit and, connected to one or more of the components, single-pin imaginary devices associated with group properties of the components. The method further includes automatically generating a design layout for the circuit based on the schematic diagram. The design layout comprises shapes representing the components and, on each shape representing a specific component that is connected to a single-pin imaginary device, a specific group label corresponding to a specific group property of the specific component. Placement of the shapes within the design layout is group label dependent. Accessing of the schematic diagram and the automatically generating of the design layout are performed by a layout generator tool executed by a processor of a computer-aided design system.

Abstract: Method, apparatus and computer program product for hierarchical power analysis using improved activity abstraction and capacitance abstraction by accounting for design heterogeneity extremities comprising extracting design heterogeneity extremities from an RTL design; accounting for the design heterogeneity extremities during macro clock and data signals activity abstraction to generate improved macro activity abstractions; accounting for the design heterogeneity extremities during macro clock and data switching capacitance abstraction to generate improved macro capacitance abstractions; and using improved macro activity abstractions and improved macro capacitance abstractions during hierarchical chip power analysis.

Abstract: Systems and methods to implement performance monitoring of a device under test involve defining one or more sequences. Each of the one or more sequences includes two or more events, each of the two or more events being defined by one or more hardware signals that include a hardware register value, transmission of a message or signal, or a wire voltage change. A method includes initiating a simulation of the device under test by inputting one or more signals at one or more inputs of the device under test for propagation across the device under test, and monitoring completion of the two or more events defining each of the one or more sequences. Performance of the device under test is reported. Reporting includes providing latency of each of the one or more sequences. A final design of the device under test is provided for fabrication based on the performance monitoring.

Abstract: A synergistic design method for an integrated circuit (IC) is provided. The synergistic design method includes forming a standard cell library and a non-standard cell library, implementing an IC design process from a high-level behavior specification through a gate-level netlist to a physical layout, and verifying the physical layout to fabricate the IC. Each standard cell of the standard cell library performs a Boolean logic operation. Each non-standard cell of the non-standard cell library performs a complex function beyond the Boolean logic operation. A conversion process is executed for translating a circuit function into a Boolean network to generate the gate-level netlist based on the standard cells of the standard cell library corresponding to the circuit function. A direct mapping is executed on the non-standard cell by skipping the conversion process during the IC design process to generate the gate-level netlist.

Abstract: Methods and example implementations described herein are generally directed to the addition of networks-on-chip (NoC) to FPGAs to customize traffic and optimize performance. An aspect of the present application relates to a Field-Programmable Gate-Array (FPGA) system. The FPGA system can include an FPGA having one or more lookup tables (LUTs) and wires, and a Network-on-Chip (NoC) having a hardened network topology configured to provide connectivity at a higher frequency that the FPGA.

Abstract: An approach is described for a method, system, and product for detection of contours for data pads of a device having a free form contour, clustering integrated circuit pads and data pads, performing any angle routing based on a contour angle, and performing resistance balancing. For example, data pads of a display device having one or more curved contours (e.g. data pads arranged on an arc) are identified. Corresponding data pads and integrated circuit pads are then grouped together for routing interconnections and subsequently routed using any angle routing instead of merely routing interconnections with turns having 90-degree or 45-degree angles. Finally, the routed interconnects may be further refined/modified to balance resistances of the interconnections.

Abstract: The present disclosure relates to a method of a mask layout, including: providing a frame with preset areas arranged at intervals, a positioning area between two adjacent preset areas, and a fixed area provided to offset from the positioning area and each of the preset areas, and a distance between two adjacent preset areas being a first predetermined distance L1; providing a cover mask corresponding to the positioning area, and a distance between an edge of the cover mask and the center of the positioning area being a second predetermined distance L2; and providing an evaporation mask on the fixed area according to preset conditions, a distance between two adjacent fixed areas being a third predetermined distance L3, and the third predetermined distance L3 being equal to a difference between the first predetermined distance L1 and the second predetermined distance L2.

Abstract: An electronic device and a method thereof, which supports fast wireless charging, are provided.

Abstract: The disclosure provides a method and apparatus for designing a resistive random access memory, and the method comprise: receiving a preset first parameter standard of a resistive switching material, searching for and outputting a first resistive switching material based on the first parameter standard, first parameters including: band gap, charge transfer, vacancy, migration barrier, carrier activation energy.

Abstract: Systems, methods, and devices are described herein for integrated circuit (IC) layout validation. A plurality of IC patterns are collected which include a first set of patterns capable of being manufactured and a second set of patterns incapable of being manufactured. A machine learning model is trained using the plurality of IC patterns. The machine learning model generates a prediction model for validating IC layouts. The prediction model receives data including a set of test patterns comprising scanning electron microscope (SEM) images of IC patterns. Design violations associated with an IC layout are determined based on the SEM images and the plurality of IC patterns. A summary of the design violations is provided for further characterization of the IC layout.

Abstract: Provided is a charger with a battery diagnosis function and a control method thereof. The charger with a battery diagnosis function includes a DC-DC converter configured to operate in a charging mode to charge a battery or to operate in a diagnosing mode to apply a perturbation voltage to the battery when the battery is fully charged, and a digital signal processor configured to calculate an equivalent circuit model parameter of the battery according to an output response of the battery with respect to the perturbation voltage, to calculate a charging/discharging frequency of the battery by using an ohmic resistance value among the equivalent circuit model parameter of the battery, and to calculate a residual equivalent capacity of the battery by using the charging/discharging frequency of the battery.