Abstract: The present embodiments relate to implementing an integrated circuit design where a layout of circuit cells on a semiconductor chip is based on positions of the circuit cells on a schematic. According to some aspects, embodiments relate to a method for identifying a plurality of sub-regions on a semiconductor chip layout where each sub-region has a placement constraint. The method further includes assigning circuit cells to sub-regions based on the constraints. The method also includes clustering the circuit cells into clusters based on their positions on the schematic. Circuit cells from each cluster are placed in one or more of the sub-regions based on the proximity of the centers of the clusters to the centers of the sub-regions.

Abstract: An example includes accessing multiple configurations stored in a memory, where each configuration is associated with a corresponding circuit function implementable by an electronic device and associated with a corresponding set of resources of the electronic device. The example includes determining that one or more sets of resources of the electronic device are available for use by one or more configurations of the multiple configurations. Based on the determination, an embodiment includes representing a first configuration of the one or more configurations, using a graphical interface, and generating instructions that when executed cause the electronic device to be configured according the first configurations.

Abstract: In some embodiments, data is received defining a plurality of shot groups that will be delivered by a charged particle beam writer during an overall time period, where a first shot group will be delivered onto a first designated area at a first time period. A temperature of the first designated area at a different time period is determined. In some embodiments, the different time period is when secondary effects of exposure from a second shot group are received at the first designated area. In some embodiments, transient temperatures of a target designated area are determined at time periods when exposure from a shot group is received. An effective temperature of the target area is determined, using the transient temperatures and applying a compensation factor based on an amount of exposure received during that time period. A shot in the target shot group is modified based on the effective temperature.

Abstract: A system and method for generating standard delay format (SDF) files is disclosed. For each timing closed hierarchical instance, timing arcs on internal register to register paths may be marked as zero delay arcs. If the zero delay causes a hold violation, an adjustment may be computed to fix the violation. If the adjustment does not cause a setup violation, the adjustment may be applied to the end point register.

Abstract: A method of determining electromigration (EM) compliance of a circuit is performed. The method includes providing a layout of the circuit, the layout comprising one or more metal lines, and changing a property of one or more of the one or more metal lines within one or more nets of a plurality of nets in the layout. Each of the nets includes a subset of the one or more metal lines. The method also includes determining one or more current values drawn only within the one or more nets and comparing the determined one or more current values drawn with corresponding threshold values. Based on the comparison, an indication is provided whether or not the layout is compliant. A pattern of the one or more metal lines in the compliant layout is transferred to a mask to be used in the manufacturing of the circuit on a substrate.

Abstract: A routing specification is received for nets of an integrated circuit connecting source cells and sink cells in the integrated circuit. A target performance parameter is received for each of the nets, the target performance parameters specifying a propagation property of electrical signals in the nets. Layouts of the nets are generated according to the routing specification. An actual performance parameter for each of the nets in the layouts is generated, in which the actual performance parameters specify a calculated actual propagation property of electrical signals in the nets. A deviation parameter is generated for each of the performance parameters. Each of the deviation parameters is indicative of a degree of deviation of the respective actual performance parameter from its target performance parameter.

Abstract: A routing specification is received for nets of an integrated circuit connecting source cells and sink cells in the integrated circuit. A target performance parameter is received for each of the nets, the target performance parameters specifying a propagation property of electrical signals in the nets. Layouts of the nets are generated according to the routing specification. An actual performance parameter for each of the nets in the layouts is generated, in which the actual performance parameters specify a calculated actual propagation property of electrical signals in the nets. A deviation parameter is generated for each of the performance parameters. Each of the deviation parameters is indicative of a degree of deviation of the respective actual performance parameter from its target performance parameter.

Abstract: In one embodiment, a generating method of drawing data includes generating a pixel map that includes dose amount information on each of pixels obtained by dividing a drawing area on an object into a mesh, extracting, from the pixel map, an island-shaped pixel map which is a group of multiple pixels in which the dose amount information is not zero, determining an order of definition of the dose amount information on the pixels in the island-shaped pixel map, and generating a compressed pixel map including a size of the pixels, information indicating the order of definition, coordinates of a pixel which is first in the order of definition in the island-shaped pixel map, and the dose amount information on the pixels in the island-shaped pixel map, the dose amount information being continuously defined based on the order of definition.

Abstract: A cell layout includes a first cell having a plurality of first poly lines extending along a first direction, a second cell having a plurality of second poly lines extending along the first direction, and a boundary cell contiguous with the first cell. The first poly lines have a first uniform poly pitch and the second poly lines have a second uniform poly pitch. The second uniform poly pitch is smaller than the first uniform poly pitch. The boundary cell includes n stripes of first dummy poly lines and m stripes of second dummy poly lines extending along the first direction. The first dummy poly lines have the first uniform poly pitch and the second dummy poly lines have the second uniform pitch.

Abstract: A method for generating masks for manufacturing of a semiconductor structure includes the following steps. First, a design pattern is provided to a processor. The design pattern includes at least one first pattern and at least two second patterns shorter than the first pattern, wherein two of the second patterns are arranged in a line along an extending direction of the patterns. Then, the second patterns are elongated by the processor such that the two second patterns arranged in the line are separated from each other by a distance equal to a minimum space of the design pattern. The design pattern is divided into a first set of patterns and a second set of patterns by the processor. A first mask is generated by the processor based on the first set of patterns. A second mask is generated by the processor based on the second set of patterns.

Abstract: A system for facilitating communication between a vehicle and a user includes a vehicle having a rechargeable battery and a communication and control subsystem. The communication and control subsystem is communicatively coupled to the battery to gather and transmit vehicle information, which may include battery information and a vehicle identifier. The system also includes a charging station having a charging station identifier and an electrical coupling between the charging station, a power source, and the vehicle. The electrical coupling is operable to charge the battery and includes a communicative coupling. The control subsystem is operable to receive communications from the user via the communicative coupling.

Abstract: A transmission amplifier is provided for amplifying the signal in a wire-free transmission system. The transmission amplifier includes a pre-amplifier stage and an amplifier output stage that is coupled to the pre-amplifier stage. The amplifier output stage is configured with gate components and is configured to provide a signal fed in as an amplified output signal on the output side.

Abstract: A system for integrated computational element (“ICE”) design optimization and analysis utilizes a genetic algorithm to evolve layer thickness of each fixed ICE structure using a constrained multi-objective merit function. The system outputs a ranked representative group of ICE design candidates that may be used for further fabricability study, ICE combination selection, efficient statistical analysis and/or feature characterization.

Abstract: The present disclosure includes a method of charging a battery. In one embodiment, the method comprises receiving, in a battery charging circuit on an electronic device, an input voltage having a first voltage value from an external power source. The battery charger is configured to produce a charge current having a first current value into the battery. The input current limit and/or duty cycle of the charger is monitored. Control signals may be generated to increase the first voltage value of the input voltage if either (i) the input current limit is activated or (ii) the duty cycle reaches a maximum duty cycle. The charger also receives signals indicating a temperature inside the electronic device and generates control signals to decrease the value of the input voltage when the temperature increases above a threshold temperature.

Abstract: Aspects describing modified self-aligned quadruple patterning (SAQP) processes using cut pattern masks to fabricate integrated circuit (IC) cells with reduced area are disclosed. In one aspect, a modified SAQP process includes disposing multiple mandrels. First spacers are disposed on either side of each mandrel, and second spacers are disposed on either side of each first spacer. A cut pattern mask is disposed over the second spacers and includes openings that expose second spacers corresponding to locations in which voltage rails are to be disposed. The voltage rails are formed by removing the second spacers exposed by the openings in the cut pattern mask, and disposing the voltage rails in the corresponding locations left vacant by removing the second spacers. Routing lines are disposed over routing tracks formed between each set of the remaining second spacers to allow for interconnecting of active devices formed in the IC cell.

Abstract: A method of forming at least one Micro-Electro-Mechanical System (MEMS) includes forming a beam structure and an electrode on an insulator layer, remote from the beam structure. The method further includes forming at least one sacrificial layer over the beam structure, and remote from the electrode. The method further includes forming a lid structure over the at least one sacrificial layer and the electrode. The method further includes providing simultaneously a vent hole through the lid structure to expose the sacrificial layer and to form a partial via over the electrode. The method further includes venting the sacrificial layer to form a cavity. The method further includes sealing the vent hole with material. The method further includes forming a final via in the lid structure to the electrode, through the partial via.

Abstract: Transient voltage noise, including resistive and reactive noise, causes timing errors at runtime. A heuristic framework, Walking Pads, is introduced to minimize transient voltage violations by optimizing power supply pad placement. It is shown that the steady-state optimal design point differs from the transient optimum, and further noise reduction can be achieved with transient optimization. The methodology significantly reduces voltage violations by balancing the average transient voltage noise of the four branches at each pad site. When pad placement is optimized using a representative stressmark, voltage violations are reduced 46-80% across 11 Parsec benchmarks with respect to the results from IR-drop-optimized pad placement. It is shown that the allocation of on-chip decoupling capacitance significantly influences the optimal locations of pads.

Abstract: According to one embodiment, a method, computer system, and computer program product for creating a plurality of process parameters in a circuit design is provided. The present embodiment of the invention may include receiving one parasitic extraction per layer of a circuit is used to obtain a resistance base factor and a capacitance base factor. The embodiment may further include performing Monte Carlo simulations to determine distributions of capacitance and resistance for each metal layer of the circuit, and creating scalars that scale each of the resistance base factor and the capacitance base factor to a minimum and maximum process limit. Additionally, the embodiment may include defining at least one delay corner using the created scalars, and receiving the results of one or more timing analyses performed using the resistance base factor and the capacitance base factor, and the defined delay corner to determine a delay variability per layer.

Abstract: A method including evaluating a configuration of a device for a selected device parameter and determining a value of the selected device parameter in a first optimal configuration that improves a performance of the device is provided. The method includes determining a sensitivity of the performance of the device relative to the value of the selected device parameter and determining a performance metric that differentiates the first optimal configuration with a second optimal configuration based on the sensitivity of the performance of the device. The method includes ranking the first optimal configuration and the second optimal configuration based on the performance metric and simulating the performance of the device with a second device parameter in one of the first optimal configuration or the second optimal configuration, based on the ranking. A system and a computer readable medium to perform the above method are also provided.

Abstract: Aspects of the disclosure are directed to reducing clock-ungating induced voltage droop by determining a maximum frequency value associated with an output clock waveform; modulating a clock frequency of the output clock waveform for a first time duration based on a first programmable mask pattern or a first Boolean function; and determining if either the first programmable mask pattern or the first Boolean function should be changed. In accordance with one aspect, a voltage droop mitigation circuit includes a control logic for receiving an input clock waveform and a clock enable signal waveform and for outputting a gated clock enable signal waveform; a latch coupled to the control logic, the latch for holding a state of the gated clock enable signal waveform and a AND gate coupled to the latch, the AND gate for outputting an output clock waveform.