Abstract: A battery protection system, comprising: a first protection circuit configured to detect a battery output voltage value and to disconnect the battery output from a load when the output voltage falls below a first threshold; a second protection circuit configured to detect the battery output voltage value and to disconnect the battery output from the load when the output voltage falls below a second threshold, wherein the first threshold is within a tenth of a volt of the second threshold.

Abstract: To irradiate a target with a beam of energetic electrically charged particles, the beam is formed and imaged onto a target, where it generates a pattern image composed of pixels. The pattern image is moved along a path on the target over a region of exposure, and this movement defines a number of stripes covering said region in sequential exposures and having respective widths. The number of stripes are written parallel to each other along a general direction, which is at a small angle to a principal pattern direction of structures to be written within the region of exposure.

Abstract: A technique and method for determining a process dose for a beam lithography process includes accessing a data set that enables associating (i) a plurality of measured dimensions of features exposed by beam lithography with (ii) a plurality of different exposure doses, wherein the features were exposed with the different exposure doses, and with (iii) at least one of a plurality of different densities of the exposed features and a plurality of different nominal dimensions of the exposed features. The method also includes providing a model that is parameterized in at least the following parameters (i) measured feature dimension; (ii) exposure dose; (iii) at least one of feature density and nominal feature dimension; (iv) process dose; and (v) at least one process bias. In a further step, the method includes fitting the model with the data set to determine the process dose and the process bias.

Abstract: A control method for a swappable battery pack set of electric vehicles (EVs), wherein each of the EVs has a main battery pack set and at least a swappable battery pack set simultaneously. The control method includes the following process of uninstalling the swappable battery pack set from a first EV, before charging the swappable battery pack set; executing a charge unlocking process, before charging the swappable battery pack set; executing a charge locking process, after charging the swappable battery pack set; and installing the swappable battery pack set to a second EV after executing the charge locking process.

Abstract: Systems, methods, media, and other such embodiments are described for placement of cells in a multi-level routing tree, where placement of a mid-level parent node between a grandparent node and a set of child nodes is not set. One embodiment involves generating a first routing subregion between a first set of child nodes associated with a first grandparent node and a first connecting route from the first routing subregion to the first grandparent node, which together are set as a first routing region comprising the first routing subregion and the first connecting route. Sampling points are selected along the first routing region, and for each sampling point a set of operating values associated with the sampling point is calculated. A position for the parent node is selected based on the operating values for the sampling points.

Abstract: A hybrid electric vehicle having one or more controllers, voltage-current sensors, and batteries, which are configured to generate and respond to power signals that communicate vehicle operating and start-up conditions, among other parameters and data. The components also are enabled to detect vehicle and battery conditions that include an open circuit voltage (OCV), current, differentiated current (DFC), and near zero current (NZC). The controller(s) are further configured to generate a predicted battery state of charge (SoC) from a combination of the OCV, current, DFC, NZC, and other parameters, which are calibrated according to respective magnitudes and noise calibration factors, which enables the controller(s) to charge and discharge the battery according to the predicted SoC.

Abstract: A computer implemented method for decomposing a layout of a portion of an integrated circuit is presented. The layout includes a first multitude of polygons. The method includes constructing, using the computer, a first matrix representative of a first multitude of constraints. Each of the first multitude of constraints is between a different pair of the first multitude of polygons. The method includes solving, using the computer, the first matrix to thereby assign one of a multitude of masks to each different one of the first multitude of polygons, when the computer is invoked to decompose the layout.

Abstract: An apparatus and a method is provided. The apparatus includes a polynomial generator, including an input and an output; a first matrix generator, including an input connected to the output of the polynomial generator, and an output; a second matrix generator, including an input connected to the output of the first matrix generator, and an output; a third matrix generator, including a first input connected to the output of the first matrix generator, a second input connected to the output of the second matrix generator, and an output; and a convolution generator, including an input connected to the output of the third matrix generator, and an output.

Abstract: Systems and methods are disclosed for storing dynamic layer content in a design file. A design file is received having design data corresponding to a plurality of process layers. A geometric operation formula is also received. A processor generates a polygon having dynamic layer content that is formed by applying the geometric operation formula on two or more of the plurality of process layers. The updated design file is stored, the design file now having a polygon having dynamic layer content.

Abstract: The present disclosure relates to a method for electronic design verification. Embodiments may include receiving, using at least one processor, an electronic design and identifying one or more assumptions associated with the electronic design that are mutually in conflict. Embodiments may further include grouping the one or more assumptions that are mutually in conflict into a conflicting group of assumptions and iteratively disabling at least one of the conflicting group of assumptions. Embodiments may include generating at least one trace pair depicting a scenario where an assumption from a disabled set holds in a first trace but is violated in a second trace. Embodiments may further include identifying at least one signal associated with the first trace and at least one signal associated with the second trace and comparing the at least one signal associated with the first trace and the at least one signal associated with the second trace.

Abstract: We present a Boolean logic optimization framework based on Majority-Inverter Graph (MIG). An MIG is a directed acyclic graph consisting of three-input majority nodes and regular/complemented edges. Current MIG optimization is supported by a consistent algebraic framework. However, when algebraic methods cannot improve a result quality, stronger Boolean methods are needed to attain further optimization. For this purpose, we propose MIG Boolean methods exploiting the error masking property of majority operators. Our MIG Boolean methods insert logic errors that strongly simplify an MIG while being successively masked by the voting nature of majority nodes. Thanks to the data-structure/methodology fitness, our MIG Boolean methods run in principle as fast as algebraic counterparts. Experiments show that our Boolean methodology combined with state-of-art MIG algebraic techniques enable superior optimization quality.

Abstract: A method of modifying a power mesh includes measuring distances between end cap blocks included in a standard cell in a chip sub-block. The end cap blocks are located at edges of the chip sub-block and edges of the macro cell. The method includes searching a logic circuit block located between the first and second end cap blocks of the end cap blocks. A distance between the first and second end cap blocks is shorter than a predetermined length. It is determined whether a power supply voltage line and a ground voltage line exist at a partial region of the first power mesh layer. When the power supply voltage line or the ground voltage line is determined not to exist at the partial region, the power mesh data are modified to supplement the power supply voltage line or the ground voltage line at the partial region.

Abstract: A new approach is proposed to support layout objects selection and replication via a graphic-based layout editing tool running on a host. Specifically, the graphic-based layout editing tool presents a plurality of layout objects in a layout on a display of the host and enables a user to directionally and continuously move a cursor across the layout along a single line, wherein the single line intersects with and selects a starting group of one or more layout objects. The graphic-based layout editing tool then retrieves metadata and/or design rules associated with the starting group selected layout objects and to create an expanded group of layout objects by replicating and including one or more of the layout objects in the starting group selected layout objects. The graphic-based layout editing tool then presents the expanded group of layout objects on the display following the layout objects replication operation.

Abstract: Two or more color data can be combined to form a new data source to enhance sensitivity to defocus signal. Defocus detection can be performed on the newly formed data source. In a setup step, a training wafer can be used to select the best color combination, and obtain defocus detection threshold. This can include applying a segment mask, calculating mean intensities of the segment, determining a color combination that optimizes defocus sensitivity, and generating a second segment mask based on pixels that are above a threshold to sensitivity. In a detection step, the selected color combination is calculated, and the threshold is applied to obtain defocus detection result.

Abstract: A method of analyzing an integrated circuit, which is implemented by a computing system or a processor, wherein an interconnection of a first net of the integrated circuit includes at least one conducting segment corresponding to one wiring layer or one via, includes receiving a plurality of resistances and a plurality of capacitances, which correspond to the first net, based on a process variation, counting a number of conducting segments corresponding to the first net, and calculating a first resistance or a first capacitance of the first net, based on the number of conducting segments, the plurality of resistances, and the plurality of capacitances.

Abstract: Disclosed aspects relate to facilitating system design based on unified chip specification. It can be determined based on the system design that a first interface of a first chip is to be connected to a second interface of a second chip. Then a first configuration of the first interface and a second configuration of the second interface are determined based on a unified specification. The unified specification at least specifies configurations of a plurality of chip interfaces for respective usages. A hardware design may be automatically generated based on the first and second configurations. The hardware design may include a hardware-level connection between the first and second interfaces.

Abstract: According to one aspect, embodiments of the invention provide a CDC simulation system comprising a timing analysis module configured to receive a circuit design, analyze the circuit design to identify at least one CDC, and generate a report including information related to the at least one CDC, a CDC simulation module configured to communicate with the timing analysis module and to receive the report from the timing analysis module, and a test bench module configured to communicate with the CDC simulation module, to receive the circuit design, and to operate a test bench code to simulate the operation of the circuit design, wherein the CDC simulation module is further configured to edit a top level of the test bench code, based on the received report, such that the test bench module is configured to identify timing violations in the circuit design due to the at least one CDC.

Abstract: An intelligent charging system comprises a first switching element, a phase detecting device, a current detecting device and a controller. The first switching element is turned on or off based on a first control signal. The phase detecting device is configured to determine an allowable phase time interval of a phase of a power source. The current detecting device is connected to the first switching element. The current detecting device is configured to detect a first turned on time point when the first switching element is turned on. The controller is connected to the phase detecting device and the current detecting device. The controller is configured to determine whether the first turned on time point is within the allowable phase time interval. If the first turned on time point is not within the allowable phase time interval, the controller resets a first control parameter of the first control signal.

Abstract: Methods, systems and hardware monitors for verifying that an integrated circuit defined by a hardware design meets a power requirement including detecting whether a power consuming transition has occurred for one or more flip-flops of an instantiation of the hardware design; in response to detecting that a power consuming transition has occurred, updating a count of power consuming transitions for the instantiation of the hardware design; and determining, whether the power requirement is met at a particular point in time by evaluating one or more properties that are based on the count of power consuming transitions.

Abstract: A method of forming conductive lines in a circuit is disclosed. The method includes arranging a plurality of signal traces in a first set of signal traces and a second set of signal traces, fabricating, using a first mask, a first conductive line for a first signal trace of the first set of signal traces and fabricating, using a second mask, a second conductive line for a second signal trace of the second set of signal traces. Each signal trace of the first set of signal traces has a first width. Each signal trace of the second set of signal traces has a second width different from the first width. The arranging is based on at least a length of a signal trace of the plurality of signal traces.