Abstract: A method of producing a compound semiconductor wafer which comprises cleaning the surface of a monocrystalline substrate of a group-IV element semiconductor by ion beam etching in a high vacuum, separately evaporating materials consisting of or containing the component elements of a desired compound semiconductor, jetting the vapors of the component elements into the high vacuum region to form clusters, ionizing the clusters to form cluster ions, and accelerating the cluster ions to make them impinge on the substrate so that an epitaxial layer of the desired compound semiconductor may be formed on the substrate.

Abstract: A process is provided for the VPE growth of III/V compounds such as Al.sub.x Ga.sub.1-x As in which the group III elements are transported into the reaction zone in the form of organometallic compounds in the presence of a gaseous halogen or hydrogen halide such as hydrogen chloride (HCl).

Abstract: A method of producing epitaxial semiconductor monocrystal materials of silicon carbide with the silicon carbide crystals being grown by crystallizing sublimed silicon carbide vapors.

Abstract: A method of producing a semiconductor device, comprising the steps of forming a polycrystalline semiconductor layer on the exposed surface of a single crystalline semiconductor substrate, the substrate containing an impurity of one conductivity type and the polycrystalline layer an impurity of the other conductivity type, and heating the polycrystalline layer for the activation thereof at a temperature substantially preventing the impurity contained therein from being diffused into the substrate. The crystal of the substrate is kept free from lattice defect since the impurity is not diffused thereinto. In addition, this method prevents a short circuit from occurring between semiconductor regions of differing conductivity types which would otherwise be caused by deviation in the location of a mask used in the photoetching step.

Abstract: During the manufacture of an I.sup.2 L device, to achieve diffusion steps for a collector region and a collar region at the same time, polycrystal silicon is deposited over the whole surface of the collector region and then an impurity is diffused simultaneously into the collector region and the collar region.

Abstract: A layer of epitaxial silicon is grown on a silicon growth substrate, a thin layer of silicon dioxide or other suitable insulator is grown (in the case of silicon dioxide) or deposited (for other insulators) on the epitaxial layer, and a thick layer of polysilicon is grown on the dioxide layer. The silicon growth substrate is then removed, and the epitaxial layer is etched to form islands on the insulator layer. Some of the islands are doped to form an array of infrared sensitive detectors, and a large island is doped to act as CCD region. Electrical leads are fabricated, some to provide drive and output lines for the CCDs, other to provide connections of the detectors to respective CCDs, and yet others to provide common leads for the detectors.

Abstract: The invention relates to a method for the production of extremely flat silicon troughs in a silicon substrate for MOS-transistors. The object is generally achieved by a localized etching process resulting in a slightly anisotropic trough characteristic and a subsequent rate controlled filling by a selection epitaxy process of said trough with a silicon material. The process is found to minimize the deleterious non-uniformities inherent in the prior art.

Abstract: An integrated circuit having a substrate of a first conductivity type, a first layer of opposite conductivity type thereon and a second layer of said first conductivity type inversely graded on said first layer and including a heavily doped region adjacent the surface opposite said first layer. A ring of said opposite conductivity type extends through said second layer and partially into said first layer and a diffused region of said opposite conductivity type is in the surface of said second layer.The method of fabrication includes epitaxially forming said first layer on said substrate, expitaxially forming said second layer on said first layer having a decreasing impurity concentration from the P-N junction to the surface, forming said ring, nonselectively diffusing to increase the impurity concentration at the area adjacent the surface of said second layer and selectively diffusing to form said diffused surface region.

Abstract: Disclosed is a method of isolating portions of integrated circuits which permits closely packed structures. A semiconductor wafer is provided with a substrate of one conductivity type, a first layer of opposite conductivity type and high impurity concentration formed thereon, and a second layer of either conductivity type but lower concentration formed over the first layer. The major surfaces of the semiconductor layers are parallel to the (110) plane. Narrow grooves with sidewalls in the (111) plane are etched into the first layer. A shallow diffusion of impurities of the same conductivity type as the first layer is performed in the sidewalls and bottom of the grooves which permits the first layer to be contacted from the surface of the second layer. The groove is then etched further until it extends into the underlying substrate. Impurities of the same conductivity type as the substrate are diffused into the bottom and sidewalls of the grooves.

Abstract: Process for the manufacture of MOS devices by providing wafer of P-semiconductor grade silicon in a deposition reactor. The wafer is heated to a temperature of approximately 950.degree. C. while subjecting the wafer to dry oxygen gas to produce between a very thin layer (50-250A) of silica (SiO.sub.2) on a surface of the wafer. While elevating the temperature of the wafer to approximately 1000.degree. C., the chamber is purged with nitrogen and then hydrogen gas. After an introduction of carbon dioxide gas into the chamber, silane (SiH.sub.4) or dichlorosilane gas is bled into the chamber. The silane reacts with the CO.sub.2 to deposit SiO.sub.2 on the previously formed thermal SiO.sub.2. The two layers of SiO.sub.2 may then be annealed to provide a highly coherent, defect-free gate oxide for MOS integrated circuits.

Abstract: Semiconductor segments are embedded in a crystalline substrate. Each of the segments are insulated from each other and from the substrate so that they can be used in fabricating semiconductor devices.

Abstract: A method of manufacturing a semiconductor device, in particular a device having two complementary insulated gate field effect transistors, in which an aperture is provided in a masking layer and in said aperture a zone is diffused in the body from a highly doped layer, in particular a phosphorus glass layer. According to the invention, a thermal oxide layer is formed in the aperture in a first heating step during the diffusion, after which the doping layer is removed without using a mask and while maintaining the thermal oxide layer, and the dopant is then further diffused in a second heating step. The thermal oxide layer serves as a partial masking against the diffusion, as an etchant stopper and in many cases also as a mask against ion implantation.

Abstract: The invention relates to a method in which a system of layers with a contact layer of gallium arsenide is formed epitaxially. In a second epitaxy treatment a layer of gallium aluminum arsenide is formed selectively. In order not to form the latter layer on the contact layer of gallium arsenide, the latter is shielded from gallium aluminum arsenide by means of a masking layer having a composition which differs from that of the layer to be provided selectively, so that the masking layer can afterwards be removed selectively.

Abstract: An integrated injection logic circuit, wherein the inverted, multi-collector transistor of each cell includes active base regions separated by dielectric isolation, and wherein a heavily-doped channel-stop layer is selectively located along the sidewalls of the isolation, to prevent collector-to-emitter surface inversion leakage. The isolated geometry substantially reduces parasitic capacitance between the substrate and the extrinsic base, thereby increasing the switching speed of the device.

Abstract: The invention relates to a method of manufacturing a semiconductor device in which a compound consisting of at least two semiconductor materials and having an energy gap which is smaller than that of a substrate is deposited epitaxially on the substrate. According to the invention, the composition of the mixture is determined during the deposition by means of measurement of the thermal emission.

Abstract: A single crystal of Al.sub.2 O.sub.3 is epitaxially grown on an Si-single crystal of a semiconductor device by a vapor growth method. This vapor growth method employs starting materials of HCl, Al and CO.sub.2. Further, this method advantageouslyemploys a carrier gas to carry the gaseous product of the reaction of HCl with Al. An apparatus for the production of the above-mentioned semiconductor device comprises a chamber means for the reaction of the gaseous product and the single crystal, a reaction chamber for the reaction of Al and HCl, and an introducing tube for introducing CO.sub.2 in the proximity of the Si-single crystal.

Abstract: A method for fabricating self-aligned regions of semiconductor devices such as bipolar or field effect transistors using three masking layers which are selectively etchable with respect to each other on the surface of the semiconductor body. A dimensional mask is deposited over the three layers so that the set of all of the self-aligned impurity regions to be formed through the surface of the body are defined by etching the upper masking layer, with the intermediate layer acting as an etch-stop. Using conventional wet or dry resist processes, each subset of similar impurity regions may then be formed selectively through the intermediate and lower layers without the need for precisely aligning any subsequent mask.

Abstract: Complementary MOS devices having spaced guard rings are fabricated by applying an oxide layer to an N substrate with an opening for doping P-type impurities to form a well, applying a nitride layer over a portion of the oxide and of the well portions, doping the area in the well between the nitride and the oxide to form P-type guard rings, masking the well and adjacent portion of the oxide, doping the area between the mask and the exposed nitride layer to form N-type guard rings and exposing the substrate to an oxidizing atmosphere to oxidize the substrate except where covered by the nitride layer. The nitride layer is removed and standard device processing is used to form complementary MOS in the areas previously covered by the nitride.

Abstract: A method for the epitaxial deposition of a semiconductor by electrical polarization of a liquid phase at constant temperature.Outside the growth time the polarization is applied in the direction of the cooling by the Peltier effect with a current density which is lower than the threshold which causes the growth and which lies near same.

Abstract: A monolithic integrated circuit is formed having semiconductor components disposed in surface regions of a semiconductor body, said regions being electrically isolated from the remaining semiconductor body by a pn-junction plane. The regions into which the semiconductor components are formed are electrically isolated by heavily doping surface areas of a substrate with phosphorus, antimony and/or arsenic impurities which are of the opposite conductivity from the substrate. After said doping, an epitaxial layer having a conductivity opposite to that of the substrate is formed over the entire substrate surface with a doping concentration lower than that of the substrate so that during subsequent high temperature processing steps, the substrate impurity out-diffuses into the epitaxial layer and the phosphorus of the heavily doped surface areas diffuses downwardly into the substrate to form a step-like pn-junction surface alternately extending into the substrate and into the epitaxial layer.