Abstract: The method comprises forming a blind hole in a sapphire substrate using a sulfur hexafluoride gas etchant and an etch mask comprising a single layer of silicon nitride. The blind holes are filled with epitaxially grown silicon and field effect transistors are laid out with their gates orthogonal to a line which is at a 45.degree. angle to a standard wafer flat, i.e. orthogonal to the projection of the "c" axis onto the "r" plane of the sapphire wafer.

Abstract: A reference diode and a method for making same are described, wherein a single wafer of semiconductive material is processed to provide a reverse PN junction acting in its breakdown region and to provide one or more forward PN junctions in electrical series with the reverse junction. A wafer of semiconductive material of one conductivity type is diffused with an impurity to form a plurality of regions of semiconductive material of opposite conductivity type. The regions are laterally displaced from each other and each forms a reverse PN junction at the interface between the region and the remainder of the wafer. An impurity is then diffused into one or more of these regions to form one or more forward PN junctions. An additional reverse PN junction is then formed between and adjacent to two of the previously formed regions.

Abstract: An alignment marker on a substrate surface is covered with polycrystalline semiconductor material during the growth of an epitaxial layer on the monocrystalline substrate. This polycrystalline material is then removed with a selective etchant to re-expose the marker for use in defining an area for processing at the epitaxial layer surface. Permits accurate alignment between buried layers and regions formed from the epitaxial layer surface. Permits provision of the marker on the substrate when it is undesirable to provide the marker on the epitaxial layer surface. Particularly advantageous for electron image projection exposure of electron-sensitive resists.

Abstract: A solar cell is comprised of (1) a Cu.sub.2 S thin film evaporated on a conductive substrate at an elevated temperature thereby growing a polycrystalline film of preferred orientation, and (2) an outer CdS layer grown epitaxially on the Cu.sub.2 S film.

Abstract: A crack free layer of GaP is epitaxially deposited on a silicon phosphide surface of a silicon substrate having an (III) orientation. The silicon substrate is prebaked on a carbide coated susceptor with palladium diffused hydrogen at about 1200.degree. C and pretreated with phosphine at about 1140.degree. C to form the silicon phosphide surface. The temperature is lowered to 800.degree.-900.degree. C in the presence of phosphine and trimethyl gallium is introduced at a ratio of 1 to 10 with the phosphine. Cracks in the gallium phosphide are prevented by roughing the bottom non-phosphide surface of the silicon substrate such that the roughed surface is under compressive stress and induces tensile stress on the phosphided surface to reduce the compressive stress reduced by gallium phosphide layer when the substrate is annealed at about 1200.degree. C.

Abstract: A buried load device in an integrated circuit extends between two regions of like conductivity isolated from each other by thick oxide and substrate comprises a channel beneath the oxide and having dimensions defined by a diffused region of opposite conductivity type. The buried channel is formed by impurity migration from an upper epitaxial layer that is oxidized to separate two regions and the connecting channel width is defined by diffused strip regions of opposite conductivity to establish a desired current-voltage relationship thereof.

Abstract: In the vapor phase epitaxy fabrication of semiconductor devices and in particular semiconductor lasers, the deposition body on which a particular layer of the laser is to be grown is preheated to a temperature about 40.degree. to 60.degree. C. lower than the temperature at which deposition occurs. It has been discovered that by preheating at this lower temperature there is reduced thermal decomposition at the deposition surface, especially for semiconductor materials such as indium gallium phosphide and gallium arsenide phosphide. A reduction in thermal decomposition reduces imperfections in the deposition body in the vicinity of the deposition surface, thereby providing a device with higher efficiency and longer lifetime.

Abstract: The method makes possible the manufacture of luminescence diodes on the basis of GaAsP or other ternary semiconductor layers deposited on a Ge substrate of n-type conductivity, followed by a zinc diffusion. In the method, a resist layer is deposited on the backside of the Ge substrate to passivate the backside to an extent such that it becomes thermally and chemically stable and does not release any Ge to the ambient atmosphere, and the front side of the Ge substrate is chemo-mechanically polished to microsmoothness. Immediately before the epitaxial deposition, the polished front side is subjected to a very weak chemical etching to a removal depth of 500 A units without eliminating the polish or microsmoothness and, thereupon, the substrate is heated, in a high purity hydrogen atmosphere, to a temperature between about 680.degree. C and 720.degree. C and a GaAs layer is deposited on the front side. The temperature is then increased and there is deposited, on the GaAs layer, a ternary A.sub.III B.sub.

Abstract: A method of growing epitaxial semiconductor films on substrates is proposed which consists in that a substrate is cleaned from damage layers and heated to a critical epitaxy temperature simultaneously by irradiating a substrate surface with an intensive luminous flux. A source material for growing a film is introduced to the substrate in a gaseous state. When producing multi-layer semiconductor structures, a substrate surface opposite to a surface exposed to the luminous flux is cooled to a temperature sufficient to prevent mutual diffusion between the film and the substrate materials. Versions of an apparatus for carrying this method into effect are also proposed. The apparatus includes a quartz chamber with a vaporizer for vaporizing the source material for film growing, a means for supporting the substrate and openings for introducing a neutral or reducing agent. The apparatus is provided with furnaces for heating the walls of the chamber.

Abstract: The invention relates to a method of manufacturing a semiconductor device in which a surface of a silicon semiconductor region covered at least partly with a silicon oxide-containing layer is subjected to a nitridation treatment forming a buried zone of a nitrogen-containing material between the silicon oxide layer and the silicon region, which zone is used in a further phase of the manufacture or in the manufactured semiconductor device.

Abstract: The specification describes a compound semiconductor solar cell and fabrication process therefor wherein both the P and N-type layers of the cell are polycrystalline semiconducting material and have large crystallites with grain boundaries of similar dimensions and spacings. These grain boundaries are spaced apart by a distance substantially greater than the optical absorption length, .LAMBDA., in one of the layers and by an amount sufficient to permit substantial numbers of photon-generated carriers in that one layer to cross the PN junction between the layers. Thus, substantial power is generated without the requirement for using expensive monocrystalline semiconductive materials.

Abstract: A process for producing large-size, substrate-based semiconductor material of silicon deposited on a substrate body from the gaseous phase, which comprises the steps of heating a substrate body by direct current passage to deposition temperature, contacting said body with a gaseous silicon-containing mixture to which a dopant has been added, until a deposit having a thickness from about 10 to 200 .mu.m has been formed, subsequently melting 80 to 100% of the deposited silicon layer from the free surface downward, and resolidifying the molten silicon by adjustment of a temperature gradient from the substrate body upward. Large-sized plates obtained by cutting up the semiconductor material are used as solar cells.

Abstract: A method is described for growing epitaxial layers of material on monocrystalline substrates, chiefly silicon, which are substantially free of slip dislocations. The method involves placing an encircling ring of inert, heat resistant material around the rim of the substrate and over the peripheral surface of the substrate to suppress radiation from the peripheral portion of the wafer. The generation of slip dislocations is inhibited because heat is more uniformly distributed throughout the wafer.

Abstract: In the production of a semiconductor integrated circuit device including a selective oxidation step at a high temperature using a nitride film as a mask for isolating respective element regions in a semiconductor wafer with oxidized regions, electrode contact regions and active regions are successively formed in each element region to be surrounded by the oxidized regions and thin oxide films are formed on exposed surfaces of the electrode contact regions, the thin semiconductor oxide films are removed simultaneously by immersed etching, and then electrode metal layers are formed thereon. The thickness of the oxide layer on which the electrode metal layers are formed is maintained almost uniform to ensure the isolation effect. Since a buried region in each element region is required only to make partial contact with the contact region at the bottom portion, the integration density of the elements in the integrated circuit can be increased.

Abstract: MBE growth of epitaxial layers on selected areas of a growth surface (e.g., wafer or epi-layer grown thereon) is achieved by masking portions of the surface with an amorphous material and directing molecular beams at the masked surface so that a polycrystalline layer deposits on the mask and an epi-layer grows in the unmasked zones. The mask material is then exposed to a suitable etchant effective to dissolve that material, lift-off the polycrystalline layer and expose the underlying surface. Self-aligned contacts can be fabricated by depositing a metal layer prior to etching. Subsequent lift-off removes both the polycrystalline layer and the overlying metal. This process can be utilized in the fabrication of FETs and opto-electronic devices such as double heterostructure junction lasers.

Abstract: The operating frequency of an IMPATT diode depends on the width of the depletion region formed during operation. The frequency of high efficiency GaAs IMPATT diodes comprising a non-uniformly doped depletion region contacted by a rectifying barrier can be more precisely fixed by forming a "clump" of charge at exactly the depth below the surface contacted by the rectifying barrier corresponding to the desired depletion region.

Abstract: A semiconductor read/write memory comprised of an array of cells, each having a single active element that is a IGFET device formed in a recess with one source or drain region located directly above and its other source or drain region located within a buried storage capacitor. The gate of each device is connected to an address line in the array, and transverse diffused bit lines interconnect the drains of the devices in aligned and spaced apart cells. Voltage applied via an address line activates a gate to charge its buried capacitor and store a signal when its connected bit line is also activated. Readout of stored charges is controlled by the address line through the connected bit line in the conventional manner.

Abstract: A process which utilizes an anodized porous silicon technique to form dielectric isolation on one side of a semiconductor device is described. Regions of silicon semiconductor are fully isolated from one another by this technique. The starting wafer typically is predominantly P with a P+ layer thereon. A P or N layer over the P+ layer is formed thereover such as by epitaxial growth. The surface of the silicon is oxidized and a photoresist layer applied thereto. Openings are formed in the photoresist. Openings are formed in the silicon dioxide using the photoresist as a mask and appropriate etching techniques. The openings in the silicon dioxide define the regions to be etched by reactive ion etching. Reactive ion etching is accomplished at least down to the P+ region. The structure is then subjected to the anodic etching technique which preferentially attacks the P+ layer to form porous silicon throughout the P+ layer.

Abstract: A method for isolating regions of silicon involving the formation of openings that have a suitable taper in a block of silicon, thermally oxidizing the surfaces of the openings, and filling the openings with a dielectric material to isolate regions of silicon within the silicon block. The method is particularly useful wherein the openings are made through a region of silicon having a layer of a high doping conductivity.

Abstract: A structure and process are disclosed for making a low-voltage breakdown p-n junction in a semiconductor substrate. The process comprises the step of etching a V-shaped groove in a semiconductor substrate of a first conductivity type, with an anistropic etchant, followed by depositing a layer of epitaxial semiconductor material of a second conductivity type in the V-shaped groove. There results a p-n junction with a small radius of curvature at the apex of the V-shaped groove having a correspondingly low breakdown voltage.