Abstract: A bearing metal for large size engines having excellent compatibility and as well as embeddability even when used under a poorly lubricated condition. Such bearing metal consists of three or four layers, including a layer of a bearing alloy which contains more than 50% and up to 65% by weight of tin, with the remainder being made up of aluminum, and which may also include less than 0.5% by weight of copper. This bearing alloy has a hardness at high temperature exceeding 100.degree. C. lying between that of aluminum-tin bearing alloys which contain up to 50% by weight of tin and that of tin base or lead base white metal bearing alloys.

Abstract: In order to decrease threshold current of a semiconductor laser, and to obtain a single mode lasing suitable for use in light-communication, the semiconductor laser is formed in stripe type in which the light-emitting (i.e., active) layer and neighboring layers are formed in mesa-etched stripe type and low impurity-concentration (i.e., high resistivity) layers of GaAs, GaAsP or GaAlAs are situated to contact the mesa-etched side faces of the stripe-shaped part on the semiconductor device by vapor phase growth, vacuum deposition, sputtering, or molecular beam deposition. Since the wafer temperature can be kept fairly low (e.g. 400.degree.-700.degree. C.) in comparison with that (about 950.degree. C.) in a liquid phase growth, the stress introduced during the deposition is smaller than that in a liquid phase growth.

Abstract: A method of spatially tailoring the surface barrier of MOS devices by means of a scanning electron microscope using ionizing radiation at the silicon dioxide-silicon interface to control the surface charge distribution. The MOS is subsequently annealed at about 300.degree. C. for several hours to stabilize the surface potential.

Abstract: Apparatus for molecular beam deposition sequentially on a plurality of substrates is described. The apparatus includes a growth chamber and an auxiliary (sample-exchange) chamber coupled by an air-lock. The substrates are carried by a rod which can be translated via a bellows mechanism between the two chambers. The auxiliary chamber includes a port which permits access to the samples so that the entire rod-bellows mechanism need not be removed in order to change samples. The auxiliary chamber also includes means for maintaining therein an inert atmosphere at a pressure in excess of atmospheric pressure especially when the port is open. The growth chamber includes a cylindrical liquid nitrogen (LN.sub.2) shroud which has an aperture in its wall to admit molecular beams to only a heated (growth) substrate. The unheated (idle) substrates are thus shaded from the beams. In addition, the shroud surrounds both the growth substrate and idle substrates in the growth chamber.

Abstract: A method of making a number of semiconductor diodes on a single wafer without breakage during handling and processing, comprising the steps of forming a plurality of mesas on one surface of an intrinsic substrate, diffusing a selected first conductivity-type region into each mesa, coating the front surface of the substrate and mesas with oxide, chemically milling recesses into the opposite side of the substrate in alignment with the mesas to a predetermined depth where the mesas are each supported by a thin annular area of substrate material permitting transfer of the device into an epitaxial reactor, gas etching the recesses to a depth beyond the oxide interface to physically separate the mesas from the substrate material, growing a thin epitaxial layer of opposite conductivity type over the back surface of the device, applying ohmic contacts to the device, and separating the individual mesas.

Abstract: A method and apparatus for depositing a monocrystalline epitaxial layer of semiconductor material, e.g., silicon containing selected conductivity-determining impurities, on a semiconductor substrate comprising directing a beam of ions of said semiconductor material at the surface of the semiconductor substrate at an energy level below 0.5 Kev., and simultaneously directing a beam of the conductivity-determining impurity ions at at least a portion of the substrate surface whereby a layer of semiconductor material containing said conductivity-determining impurities is formed on said surface, and heating said layer to a temperature of at least 550.degree. C. to render said layer monocrystalline. The beams of semiconductor ions and of conductivity-determining impurity ions are preferably maintained at a high current density of at least 1 ma/cm.sup.2 at the surface of said semiconductor substrate even with a preferable relatively broad beam having diameters of up to 15 cm.

Abstract: Epitaxial tunnels may be formed in crystalline bodies of crystalline materials by growth of the material on a substrate having two intersecting crystallographic planes that exhibit rapid epitaxial growth and by maintaining the growth until the structure forming along those planes closes, thereby producing a tunnel. P-n junction structures can be made in semiconductor devices by appropriate techniques.

Abstract: In preparing tin oxide and indium tin oxide-silicon heterojunction solar cells by electron beam sublimation of the oxide and subsequent deposition thereof on the silicon, the engineering efficiency of the resultant cell is enhanced by depositing the oxide at a predetermined favorable angle of incidence. Typically the angle of incidence is between 40.degree. and 70.degree. and preferably between 55.degree. and 65.degree. when the oxide is tin oxide and between 40.degree. and 70.degree. when the oxide deposited is indium tin oxide. giThe Government of the United States of America has rights in this invention pursuant to Department of Energy Contract No. EY-76-C-03-1283.

Abstract: A method in which a monocrystalline body is subjected in a gas atmosphere to a treatment for changing the thickness of the body, in which the thickness of the body is controlled by means of a measuring member which is subjected to the same treatment and which measuring member, on its side which is subjected to the treatment, consists of a monocrystalline layer and an adjoining substratum of a material having a refractive index differing of that the monocrystalline layer material. The measuring member is obtained by providing a substrate, depositing the monocrystalline layer on the substrate, forming the substratum on the monocrystalline layer, and then removing the substrate to form the measuring member.

Abstract: A zener diode is incorporated into a conventional integrated circuit without changing the process. The structure employed produces a diode that breaks down in a subsurface region, thus avoiding the noise and instabilities that attend surface breakdown. An isolation diffusion is employed to make the anode and an NPN transistor emitter diffusion is employed to provide the cathode. If the emitter diffusion diameter is larger than the oxide cut used to achieve isolation predeposition and is concentric therewith, the resulting zener diode will have its breakdown region confined to under the emitter diffusion. The diode action is thereby remote from surface junction breakdown effects.

Abstract: A foraminous sheet of carrier substrate is contacted, by full or partial immersion, with a bath of molten silicon to form a sheet of material in which the foramina are filled with silicon and at least one surface of the sheet is coated with silicon. The coated sheet is suitable for use in forming a photovoltaic cell.

Abstract: The invention relates to a semiconductor component element, in particular a Schottky field-effect transistor with a low series resistance, as well as a process for the production thereof.By means of a novel masking technique, it is possible for the channel region to be implanted as well as the source and drain regions, in a single implantation step. Only one photomask is necessary. By a novel masking arrangement, only a small fraction of the radiated ions get through to the region of the substrate where the channel is to be formed. This enables the formation of a Schottky contact where the channel will be formed. The source and drain regions are formed by allowing a much higher portion of the ions to reach such regions. This allows ohmic contacts to be formed on the source and drain. Thus, in the implantation of the dopant particles, regions are formed with different layer resistances in the semiconductor substrate.

Abstract: A process of manufacturing a static induction thyristor comprising providing a semiconductor substrate of the first conductivity type which defines a first semiconductor layer and forming a second semiconductor layer thereon of a second conductivity type. The first and second semiconductor layers have relative impurity concentrations effective for forming therebetween charge depletion regions when no electrical signal is applied to the second semiconductor layer and which prevent injection of charge carriers through the second semiconductor layer when the thyristor is in a blocking state, and such that electrically forward biasing the second semiconductor layer effectuates a sufficient reduction of the depletion regions that a sufficient quantity of charge carriers may be injected through the second semiconductor layer that the thryistor switches to a conductive state. The second semiconductor layer defines the gate region of the thyristor.

Abstract: A foraminous sheet of carrier substrate is formed by immersing the sheet in a bath of molten silicon. After cooling, the coated sheet is suitable for use in making a photovoltaic cell.

Abstract: A method for producing a heterogeneous semiconductor structure with a composition gradient in which a semiconductor material is transferred through the gaseous phase onto the substrate from a source comprising the two AB and AC components and including a number of parallel strips, each of said strips having a constant ratio between the AB and AC components. At first, the source is gradually brought under the substrate at a speed chosen within the range of 100 cm per hour to 0.1 cm per hour, bringing first the strip of the source, which has a maximum content of the AB component. As all the strips have been brought under the substrate, the source is stopped for a period of time required for the formation of the main layer of a required thickness.

Abstract: Three-dimensional structures having a suitable geometrical configuration are directly formed on one major surface of a substrate so that an epitaxial molecular beam may be incident on preselected regions, and the angles of incidence of epitaxial molecular beams are varied. As a result the arrival rates of molecular beams are varied from one region to another on the substrate so that a three-dimensional epitaxial layer in which the physical properties are different from one region of a submicron across to another may be grown.

Abstract: The specification describes a gallium aluminum arsenide-gallium arsenide-germanium solar cell and fabrication process therefor wherein the deposition of a layer of gallium aluminum arsenide establishes a first PN junction in the GaAs of one bandgap energy on one side of a gallium arsenide substrate, and the deposition of a layer of germanium establishes a second PN junction in Ge of a different bandgap energy on the other side of the GaAs substrate. The two PN junctions are responsive respectively to different wavelength ranges of solar energy to thus enhance the power output capability of a single wafer (substrate) solar cell. Utilization of the Group IV element germanium, as contrasted to compound semiconductors, simplifies the process control requirements relative to known prior art compound semiconductor processes, and germanium also provides a good crystal lattice match with gallium arsenide and thereby maximizes process yields.

Abstract: A semiconductor integrated circuit device includes circuit elements having relatively different performance characteristics in which buried regions having different chemical elements are used to autodope an epitaxial layer to different degrees.

Abstract: The integrated circuit is manufactured upside down relative to conventional silicon-on-sapphire (SOS) processing techniques for manufacturing field effect transistors. First a conductive pattern, typically of a refractory metal, is deposited and defined on an insulating substrate, such as sapphire, and then silicon transistors are formed over the conductive pattern. Using the process, a masking step, namely the contact definition mask, used in conventional SOS manufacture, is eliminated.

Abstract: A foraminous sheet of carrier substrate is contacted, by full or partial immersion, with a bath of molten silicon to form a sheet of material in which the foramina are filled with silicon and at least one surface of the sheet is coated with silicon. The coated sheet is suitable for use in forming a photovoltaic cell.