Abstract: In the fabrication of semiconductor devices, a method is provided which includes the steps of selectively doping a semiconductor substrate of one conductivity type to form therein discrete regions of opposite conductivity type, followed by selective epitaxial growth to fill the windows of the diffusion mask, whereby the epitaxially grown regions are inherently characterized by exact alignment with the doped regions. The self-aligned epitaxial structure is then subjected to further processing in accordance with numerous alternate schemes to provide a wide variety of devices.

Abstract: Merged transistor logic integrated circuit wherein the vertical transistor is formed by auto-doping an epitaxial silicon layer for an improved transistor doping profile. Further device improvements are achieved by the incorporation of Schottky diodes into the circuit.

Abstract: Parallel channels are separated by ridges formed in a semiconductor body in such a way that each channel is wider at its base than at its top. Molecular beam epitaxy is used to deposit semiconductor layers on the ridges and in the channels. Because each channel is narrower at its top than at its base, the configuration is essentially self-masking. That is, the layers in the channel are physically separate from those on the ridges, as would be metallic contacts deposited on the layers. This technique is employed in the fabrication of a plurality of self-aligned, stripe geometry, mesa double heterostructure junction lasers.

Abstract: Zener diodes of selectively variable breakdown voltages ranging from a few voltages to several hundred volts are fabricated in monolithic integrated circuits by locating the edge of a P-N junction at the surface of a substrate within the gradient region of P-type diffusion. Methods for making the same are also described.

Abstract: An ultraviolet light emitting diode array of aluminum nitride grown on a sapphire substrate is fabricated by sputtering a preliminary layer of aluminum nitride onto a sapphire substrate, then placing said coated substrate in contact with a source of aluminum nitride and heating said composite in a particular atmosphere, resulting in the deposition of layers of aluminum nitride onto said coated substrate.

Abstract: A method of forming buried regions in a printed circuit substrate in which; a first layer of doped silicon oxide is deposited on the substrate, a pattern of apertures is produced in this layer and a second layer of differently doped silicon oxide is deposited to fill in apertures. The first layer silicon dioxide acts as a mask to the doping material so that when the two layers are subjected to a common diffusion step both doping materials are driven into the substrate, with the second layer doping material restricted to the regions of the apertures.

Abstract: An improved field effect transistor device in a monocrystalline semiconductor body provided with source and drain regions and a gate electrode disposed over the channel between the source and drain regions wherein at least the drain region is formed of a first region where the impurity concentration increases with depth with the peak concentration being spaced inwardly from the major surface, and a second region located within the first region having a peak impurity concentration at the major surface. The drain region structure in operation promotes the current flow between the source and drain to flow deeper in the channel region and spaced from the gate dielectric layer.In the method for forming the field effect transistor, an impurity is introduced into the semiconductor body underlying at least the ultimate drain region, an epitaxial semiconductor layer deposited, and a second impurity region formed over the first region to form the drain contact.

Abstract: A method of growing superlattice crystals containing alternating layers of two semiconductor materials in which misfit and threading dislocations are eliminated by growing the layers of superlattice crystal to some thickness less than that which will generate new dislocations, and matching the average lattice parameter of the superlattice with that of substrate so misfit dislocations between the superlattice and the substrate are not formed.

Abstract: A version of integrated injection logic is disclosed in which both the switching transistor and the current source transistor are of the vertical type and in which the logic gates are fabricated in the same semiconductor integrated chip with linear circuits which are based on the complementary bipolar integrated circuit technology.The injection logic gate is fabricated simultaneously with the linear integrated circuit using selected steps of the complementary bipolar technology. High voltage linear circuits and efficient logic circuits are achieved based on the use of a single moderate resistivity N-type epitaxial layer deposited on a high resistivity P-type substrate. In the logic circuit portion the epitaxial layer forms the collector zone of the current source transistor and the base zone of the switching transistor.

Abstract: The invention relates to a method for the epitaxial growth from the gaseous phase of III-V-compounds at homogeneous and low temperature by varying the atmosphere specifically, by utilizing a neutral gas in the initial transport reaction and subsequently introducing hydrogen into the gaseous mixture in the immediate vicinity of the substrate. The temperature in the epitaxial space is homogeneous and low (600.degree. C) and the qualities of the deposited layers are considerably improved.

Abstract: Enhancement-mode field-effect transistors (FETs) and depletion-mode FETs are provided on the same semiconductive substrate using five basic, lithographic, pattern-delineating steps. The five lithographic masking steps delineate in order:(1) the field isolation regions;(2) the enhancement-mode FET gate electrodes;(3) the depletion-mode FET gate electrodes;(4) contact holes or vias to FET source and drain regions and to depletion-mode FET gates; and(5) the high electrical conductivity metallic-type interconnection pattern.The low-concentration doping required to form the depletion-mode channel regions is provided after the second but before the third pattern delineation step, while the high-concentration doping to form the source and drain regions is provided after the third pattern delineation step. In order to obtain the desired device structure, it is necessary to use two separately defined polycrystalline silicon regions for the gate electrodes of the enhancement-mode and depletion-mode FETs.

Abstract: The present invention describes the manufacture of a chip having a stratum in which a number of diffusions are spaced from each other by boundaries whose widths is the width of a gap. The diffusion on one side of a boundary is formed by ion bombardment, and that on the other side by heat transfer of ions of a material with which the film has been doped.

Abstract: A process for suppressing parasitic components, in particular parasitic diodes and transistors, in integrated circuits which have, in particular, inversely operated transistors, in which a semiconductor substrate of the first conductivity type as introduced therein a highly doped zone of a second conductivity type which is opposite to the first conductivity type and which extends to a surface of the semiconductor substrate. A semiconductor layer of the second conductivity type is epitaxially deposited on the surface and the semiconductor layer further has produced therein zones of differing conductivity type which form at least one component which is electrically insulated from adjacent components.

Abstract: Process and apparatus for heating substrates to form semiconductor regions. A gaseous reactant is introduced into a reaction chamber formed from a material, such as quartz, which is transparent and non-obstructive to radiant heat energy transmitted at a predetermined short wave length. A graphite susceptor, which is opaque to and absorbs the radiant heat energy, is positioned within the reaction chamber and supports the substrates to be processed. The susceptor and substrates are heated directly while the walls of the reaction chamber remain cool. The substrates are heated uniformly, and single crystal semiconductor wafers processed by this technique have little or no crystallographic slip. To further insure uniform heating, the susceptor may be moved relative to the radiant heat source which, in the preferred embodiment, comprises a bank of tungsten filament quartz-iodine high intensity lamps.

Abstract: A layer of epitaxial silicon is grown on an epi-silicon growth substrate, a thin silicon dioxide layer is grown on the epitaxial layer, and thick layer of polysilicon is grown on the dioxide layer. The epi-silicon layer is then removed, and the epitaxial layer is masked and doped to produce both a region capable of CCD action and an infrared sensitive region. The doped epitaxial layer is orientially etched through a mask to produce isolated infrared sensitive areas to serve as detectors and an isolated area capable of CCD action. Coupling regions are also doped on the CCD ares. The detectors and the CCD area are each in the shape of a frustum of a right rectangular pyramid, with its base on the silicon dioxide layer. Electrical pads are grown to form CCDs. Electrical leads are grown, some to connect respective CCDs to respective coupling regions, some to serve as drive lines for the CCDs, some as common lines for the detectors, and some as connecting lines between respective detectors and coupling regions.

Abstract: Low-cost polycrystalline silicon solar cells supported on substrates are prepared by depositing successive layers of polycrystalline silicon containing appropriate dopants over supporting substrates of a member selected from the group consisting of metallurgical-grade polycrystalline silicon, graphite and steel coated with a diffusion barrier of silica, borosilicate, phosphosilicate, or mixtures thereof such that p-n junction devices are formed which effectively convert solar energy to electrical energy. To improve the conversion efficiency of the polycrystalline silicon solar cells, the crystallite size in the silicon is substantially increased by melting and solidifying a base layer of polycrystalline silicon before depositing the layers which form the p-n junction.

Abstract: An integrated transistor circuit arrangement provides a multicollector transistor with Schottky diodes and ohmic connections selectively formed at the collector terminals. In the illustrative example, a vertical transistor is formed in an N-type epitaxial layer overlying an N+ substrate. A through-extending region of P+ material encircles the region of the epitaxial layer in which the vertical transistor is formed. The base of the vertical transistor is formed by the implanting of P-type impurity in a location spaced apart from the surfaces of the epitaxial layer. The resulting base has a symmetrical profile relative to the faces of the epitaxial layer. Therefore, the transistor may be operated with the collector at the surface without penalty of electrical operation. In the illustrative example, a PNP lateral transistor is utilized as a current source for the vertical transistor.

Abstract: A method of producing a siliceous cover layer on a semiconductor element or wafer so that the temperature coefficient of the cover layer is approximated to the temperature coefficient of the semiconductor wafer, comprises distributing a combined emulsion over the wafer by centrifugal force. The combined emulsion is formed by making a mixture of a first emulsion of a non-doped, pure, silica emulsion and a second emulsion of a heavily-doped silica emulsion and adjusting the ratio of the first and second emulsions so that the temperature coefficient of the formed layer will be substantially identical with the temperature coefficient of the semiconductor element in form of a wafer or die. After the cover layer is hardened, the peripheral bead which forms from the emulsion mixture is etched off so that the exposed semiconductor surface, as well as the front side of the semiconductor die or wafer, are ready for epitaxial coating.

Abstract: A method of making a junction in semiconductive materials to improve the spectral response of the junction in photovoltaic detectors. A first layer of semiconductive material is grown, by epitaxy technique, on a substrate of semiconductive material of the same conductivity type. Growth of the first layer is discontinued and the temperature is changed. Then a second layer of opposite conductivity type is grown on the first layer.

Abstract: The disclosure herein pertains to the preparation of semiconductor materials and solid-state devices fabricated therefrom. More particularly, the disclosure pertains to a vapor phase process for the preparation of electroluminescent materials, particularly GaAs.sub.1-x P.sub.x, doped with isoelectronic impurities, particularly nitrogen, and to electroluminescent devices fabricated therefrom.