Abstract: A method of manufacturing an electronic device is provided. The method comprises providing a carrier sheet, etching the lead frame material sheet to form a recess on a first surface of the lead frame material sheet, placing an electronic chip into the recess of the carrier sheet, and thereafter, selectively etching a second surface of the lead frame material sheet, the second surface being opposite to the first surface.

Abstract: The invention relates to a method 10 for forming a multi-level surface on a substrate 2, wherein said surface comprises areas of different wettability, the method comprising the step (A, B) of applying a multi-level stamp to the substrate for forming the multi-level surface, said multi-level stamp having different structural regions 1a arranged along the multi-level surface for locally altering wettability properties of at least a portion of a level of the multi-level surface 2a, 2b. The invention further relates to a semiconductor device and a method for manufacturing a semiconductor device.

Abstract: The present disclosure provides a method of manufacturing a photoelectric conversion device, including, a first step of forming a plurality of photoelectric conversion regions on a surface on one side of a semiconductor wafer, a second step of preparing a light-blocking wafer having insertion openings, a third step of bonding the one-side surface of the semiconductor wafer and a surface on the opposite side to a surface on the one side of the light-blocking wafer to each other to form a bonded wafer body, and a fourth step of dividing the bonded wafer body in peripheries of the photoelectric conversion regions, to obtain bonded-body chips each having the photoelectric conversion region.

Abstract: According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer, a second semiconductor layer and a light emitting part. The first semiconductor layer includes an n-type semiconductor layer. The second semiconductor layer includes a p-type semiconductor layer. The light emitting part is provided between the first semiconductor layer and the second semiconductor layer, and includes a plurality of barrier layers and a well layer provided between the plurality of barrier layers. The first semiconductor layer has a first irregularity and a second irregularity. The first irregularity is provided on a first major surface of the first semiconductor layer on an opposite side to the light emitting part. The second irregularity is provided on a bottom face and a top face of the first irregularity, and has a level difference smaller than a level difference between the bottom face and the top face.

Abstract: A semiconductor device includes first, second, and third semiconductor layers each having multiple diffusion layers. The first direction widths of the first diffusion layers are the same. The amount of impurity within the first diffusion layers gradually increases from the bottom end towards the top end of the first semiconductor layer. The first direction widths of the second diffusion layers are the same. The amounts of impurity within the second diffusion layers are the same. The first direction widths of the third diffusion layers are narrower than the first direction widths of the first diffusion layers and the first direction widths of the second diffusion layers at the same level, and gradually become narrower from the bottom end towards the top end of the third semiconductor layer. The amount of impurity within the third diffusion layers are the same.

Abstract: A light emitting device including a light emitting structure including a first conductive semiconductor layer, an active layer and a second conductive semiconductor layer, a first electrode disposed on the first conductive semiconductor layer, a conductive layer disposed on the second conductive semiconductor layer, a second electrode disposed on the conductive layer, a channel layer directly contacts with the light emitting structure and disposed at an adjacent region of the second electrode, a support substrate disposed on the channel layer, and wherein the conductive layer is separated into at least two unit conductive layers.

Abstract: Some embodiments include a method of forming a capacitor. An opening is formed through a silicon-containing mass to a base, and sidewalls of the opening are lined with protective material. A first capacitor electrode is formed within the opening and has sidewalls along the protective material. At least some of the silicon-containing mass is removed with an etch. The protective material protects the first capacitor electrode from being removed by the etch. A second capacitor electrode is formed along the sidewalls of the first capacitor electrode, and is spaced from the first capacitor electrode by capacitor dielectric. Some embodiments include multi-material structures having one or more of aluminum nitride, molybdenum nitride, niobium nitride, niobium oxide, silicon dioxide, tantalum nitride and tantalum oxide. Some embodiments include semiconductor constructions.

Abstract: A method for fabricating a vertical GaN power device includes providing a first GaN material having a first conductivity type and forming a second GaN material having a second conductivity type and coupled to the first GaN material to create a junction. The method further includes implanting ions through the second GaN material and into a first portion of the first GaN material to increase a doping concentration of the first conductivity type. The first portion of the junction is characterized by a reduced breakdown voltage relative to a breakdown voltage of a second portion of the junction.

Abstract: Methods of forming titanium-containing layers on substrates are disclosed. In the disclosed methods, the vapor of a precursor compound having the formula Ti(Me5Cp)(OR)3, wherein R is selected from methyl, ethyl, or isopropyl is provided. The vapor is reacted with the substrate according to an atomic layer deposition process to form a titanium-containing complex on the surface of the substrate.

Abstract: A device which includes a substrate defined with a device region with an ESD protection circuit having at least first and second transistors is disclosed. Each of the transistors includes a gate having first and second sides, a first diffusion region in the device region adjacent to the first side of the gate, a second diffusion region in the device region displaced away from the second side of the gate, and a drift isolation region disposed between the gate and the second diffusion region. A first device well encompasses the device region and a second device well is disposed within the first device well. The device also includes a drift well which encompasses the second diffusion region. Edges of the drift well do not extend below the gate and is away from a channel region. A drain well is disposed under the second diffusion region and within the drift well.

Abstract: A light emitting device with graded composition hole tunneling layer is provided. The device comprises a substrate and an n-type semiconductor layer is disposed on the substrate, in which the n-type semiconductor layer comprises a first portion and a second portion. A graded composition hole tunneling layer is disposed on the first portion of the n-type semiconductor layer. An electron blocking layer is disposed on the graded composition hole tunneling layer. A p-type semiconductor layer is disposed on the electron blocking layer. A first electrode is disposed on the p-type semiconductor layer, and a second electrode is disposed on the second portion of the n-type semiconductor layer and is electrical insulated from the first portion of the n-type semiconductor. The graded composition hole tunneling layer is used as the quantum-well to improve the transport efficiency of the holes to increase the light emitting efficiency of the light emitting device.

Abstract: The present disclosure relates to a device and method for strain inducing or high mobility channel replacement in a semiconductor device. The semiconductor device is configured to control current from a source to a drain through a channel region by use of a gate. A strain inducing or high mobility layer produced in the channel region between the source and drain can result in better device performance compared to Si, faster devices, faster data transmission, and is fully compatible with the current semiconductor manufacturing infrastructure.

Abstract: A thin-film transistor (TFT) array substrate includes a first conductive layer of a TFT, a second conductive layer that partially overlaps the first conductive layer, a through hole in a layer between the first and second conductive layers, a node contact hole integrally formed to include a first contact hole in the first conductive layer and a second contact hole in the second conductive layer such that the first contact hole is continuous with the second contact hole and is not separated from the second contact hole by an insulation layer, and a connection node that is in another layer different from the first conductive layer and the second conductive layer. The connection node is connected to the first and second conductive layers through the through hole and the node contact hole.

Abstract: A multi-chip package includes a lower substrate; at least two semiconductor chips stacked over the lower substrate and each defined with a via hole; an upper substrate coupled to a semiconductor chip positioned uppermost among the semiconductor chips; a light emitting part coupled to the lower substrate corresponding to the via hole; an electrowetting liquid lens coupled to a lower surface of the upper substrate for receiving a signal transferred from the light emitting part through the via hole; a light receiving part coupled to a sidewall of the via hole of each semiconductor chip configured to receive a signal from the electrowetting liquid lens.

Abstract: Described herein are microelectronic packages including a plurality of bonding fingers and multiple integrated circuit chips, at least one integrated circuit chip being mounted onto the bonding fingers. According to various embodiments of the present invention, mounting the integrated circuit chip onto the bonding fingers may reduce the pin-out count by allowing multiple integrated circuit chips to be interconnected within the same microelectronic package. Other embodiments may be described and claimed.

Abstract: In a manufacturing method of a solid-state image pickup device according to an embodiment, a transfer gate electrode is formed in a predetermined position on an upper surface of a first conductive semiconductor area, through a gate insulating film. A second conductive charge storage area is formed in an area adjacent to the transfer gate electrode in the first conductive semiconductor area. A sidewall is formed on a side surface of the transfer gate electrode. An insulating film is formed to extend from a circumference surface of the sidewall on a side of the charge storage area to a position partially covering the upper part of the charge storage area. A first conductive charge storage layer is formed in the charge storage area by implanting first conductive impurities from above, into the charge storage area which is partially covered with the insulating film.

Abstract: In one embodiment, a method of forming a semiconductor package includes placing a first die and a second die over a carrier. At least one of the first and the second dies are covered with an encapsulation material to form an encapsulant having a top surface and an opposite bottom surface. The encapsulant is thinned from the bottom surface to expose a first surface of the first die without exposing the second die. The exposed first surface of the first die is selectively etched to expose a second surface of the first die. A back side conductive layer is formed so as to contact the first surface. The second die is separated from the back side conductive layer by a first portion of the encapsulant.

Abstract: In a method of forming a capacitor, a first mold layer pattern including a first insulating material may be formed on a substrate. The first mold layer pattern may have a trench. A supporting layer including a second insulating material may be formed in the trench. The second insulating material may have an etching selectivity with respect to the first insulating material. A second mold layer may be formed on the first mold layer pattern and the supporting layer pattern. A lower electrode may be formed through the second mold layer and the first mold layer pattern. The lower electrode may make contact with a sidewall of the supporting layer pattern. The first mold layer pattern and the second mold layer may be removed. A dielectric layer and an upper electrode may be formed on the lower electrode and the supporting layer pattern.

Abstract: Disclosed is a light emitting device including a light emitting structure including a first conductive semiconductor layer, an active layer and a second conductive semiconductor layer, a first electrode disposed on the first conductive semiconductor layer, a reflective electrode disposed on the second conductive semiconductor layer, a channel layer disposed on the light emitting structure and surrounds the reflective electrode, and a support substrate connected to the channel layer through an adhesive layer.

Abstract: A light emitting device (10) comprises a body (12) of a semiconductor material. A first junction region (14) is formed in the body between a first region (12.1) of the body of a first doping kind and a second region (12.2) of the body of a second doping kind. A second junction region (16) is formed in the body between the second region (12.2) of the body and a third region (12.3) of the body of the first doping kind. A terminal arrangement (18) is connected to the body for, in use, reverse biasing the first junction region (14) into a breakdown mode and for forward biasing at least part (16.1) of the second junction region (16), to inject carriers towards the first junction region (14). The device (10) is configured so that a first depletion region (20) associated with the reverse biased first junction region (14) punches through to a second depletion region associated with the forward biased second junction region (16).