Abstract: When forming sophisticated high-k metal gate electrode structures, the removal of a dielectric cap material may be accomplished with superior process uniformity by using a silicon dioxide material. In other illustrative embodiments, an enhanced spacer regime may be applied, thereby also providing superior implantation conditions for forming drain and source extension regions and drain and source regions.

Abstract: An ultraviolet light absorbent silicon oxynitride layer overlies a memory cell including a pair of source/drains, a gate insulator, a floating gate, a dielectric layer, and a control gate. A conductor is disposed through the silicon oxynitride layer for electrical connection to the control gate, and another conductor is disposed through the silicon oxynitride layer for electrical connection to a source/drain.

Abstract: The present invention generally relates to a method for manufacturing an improved solar cell module, more particularly to a method for manufacturing the improved solar cell module that may not happen problems of power leakage and short circuit and save the cost to manufacturing.

Abstract: According to one embodiment, an optical semiconductor device includes an n-type semiconductor layer, a p-type semiconductor layer, and a functional part. The functional part is provided between the n-type semiconductor layer and the p-type semiconductor layers. The functional part includes a plurality of active layers stacked in a direction from the n-type semiconductor layer toward the p-type semiconductor layer. At least two of the active layers include a multilayer stacked body, an n-side barrier layer, a well layer and a p-side barrier layer. The multilayer stacked body includes a plurality of thick film layers and a plurality of thin film layers alternately stacked in the direction. The n-side barrier layer is provided between the multilayer stacked body and the p-type layer. The well layer is provided between the n-side barrier layer and the p-type layer. The p-side barrier layer is provided between the well layer and the p-type layer.

Abstract: A light emitting device according to one embodiment includes a board; plural first light emitting elements mounted on the board to emit light having a wavelength of 250 nm to 500 nm; plural second light emitting elements mounted on the board to emit light having a wavelength of 250 nm to 500 nm; a first fluorescent layer formed on each of the first light emitting elements, the first fluorescent layer including a first phosphor; and a second fluorescent layer formed on each of the second light emitting elements, the second fluorescent layer including a second phosphor. The second phosphor is higher than the first phosphor in luminous efficiency at 50° C., and is lower than the first phosphor in the luminous efficiency at 150° C.

Abstract: A junction field effect transistor structure includes a grid electrode, a source electrode, a drain electrode and a substrate. The grid electrode includes a polysilicon layer and a P-type implanted layer. The source electrode includes an N-type implanted layer, an N-type well layer and a heavy-implanted N-type well layer. The drain electrode includes the N-type implanted layer, the N-type well layer and the heavy-implanted N-type well layer. The substrate is connected with a substrate connecting end by the P-type implanted layer, a P-type well layer, a heavy-implanted P-type well layer and a P-type buried layer. The junction field effect transistor structure of the present invention can be manufactured without adding any masking step based on the existing technologies, and has the high-voltage resistant characteristic to meet the requirements in practical applications. Furthermore, it has the compact structure and compatible technology.

Abstract: A method for producing a group III nitride crystal in the present invention includes the steps of cutting a plurality of group III nitride crystal substrates 10p and 10q having a main plane from a group III nitride bulk crystal 1, the main planes 10pm and 10qm having a plane orientation with an off-angle of five degrees or less with respect to a crystal-geometrically equivalent plane orientation selected from the group consisting of {20-21}, {20-2-1}, {22-41}, and {22-4-1}, transversely arranging the substrates 10p and 10q adjacent to each other such that the main planes 10pm and 10qm of the substrates 10p and 10q are parallel to each other and each [0001] direction of the substrates 10p and 10q coincides with each other, and growing a group III nitride crystal 20 on the main planes 10pm and 10qm of the substrates 10p and 10q.

Abstract: An electrostatic discharge protection device comprises a substrate with a first conductivity, a gate, a drain structure and a source structure. The gate is disposed on a surface of the substrate. The drain structure with a second conductivity type comprises a first doping region with a first doping concentration disposed adjacent to the gate and extending into the substrate from the surface of the substrate, a second doping region extending into and stooped at the first doping region from the surface of the substrate and having a second doping concentration substantially greater than the first doping concentration, and a third doping region disposed in the substrate beneath the second doping region and having a third doping concentration substantially greater than the first doping concentration. The source structure with the second conductivity is disposed in the substrate and adjacent to the gate electrode.

Abstract: The present invention discloses a coaxial transistor formed on a substrate, particularly a coaxial metal-oxide-semiconductor field-effect transistor (CMOSFET). The chips or substrates of the CMOSFETs can be stacked up and connected via through-holes to form a coaxial complementary metal-oxide-semiconductor field-effect transistor (CCMOSFET), which is both full-symmetric and full-complementarily, has a higher integration and is free of the latch-up problem.

Abstract: A face-up optical semiconductor device can be prepared by forming an n-type GaN layer, an active layer, and a p-type GaN layer on a C-plane sapphire substrate. Parts of the p-type GaN layer and the active layer can be removed, and a transparent electrode can be formed over all or most of the remaining p-type GaN layer. A p-side electrode including a pad portion and auxiliary electrode portions can be formed on the transparent electrode layer. An n-side electrode can be formed on the exposed n-type GaN layer. On regions of the transparent electrode layer where weak light emission regions may be formed, outside independent electrodes can be provided. They can be disposed on concentric circles with the n-side electrode as a center or tangent lines thereof so as to be along the circles or the tangent lines.

Abstract: A solid-state image sensor and a method for manufacturing thereof and a semiconductor device and a method for manufacturing thereof are provided. A semiconductor substrate is made to be the thin film without using an SOI substrate and cost is reduced. An edge detection portion having hardness larger than that of a semiconductor substrate is formed in the thickness direction of the semiconductor substrate; the semiconductor substrate is made to be the thin film until a position where the edge detection portion is exposed by chemical mechanical polishing from the rear surface; and means Tr1 for reading out a signal from a photoelectric conversion element PD formed in the substrate are formed on the front surface of the semiconductor substrate, where incident light is acquired from the rear surface of the semiconductor substrate.

Abstract: A method and apparatus for a photoinduced electromotive force sensor. The sensor has an active substrate formed of a semi-insulating photoconductor with sufficient carrier trap density to form an effective charge grating and pairs of electrodes disposed on the active substrate, where the sensor is configured to reduce the photovoltaic effect caused by the incident light in the vicinity of the electrodes. The shape or composition of the electrodes may be selected to reduce the photovoltaic effect or the electrodes may be disposed on the substrate to average out the photovoltaic effect arising from each one of the electrodes.

Abstract: Provided is a side view light emitting diode package including a housing that includes a front side part and a rear side part integrally formed with the front side part, the front side part having a light emission part; and a lead frame that is located between the front side part and the rear side part, wherein the lead frame includes a first lead connected to a first electrode of a Light Emitting Diode (LED) chip and a second lead connected to a second electrode of the LED chip, wherein the front side part includes a first groove, a second groove, and a third groove, wherein the first lead and the second lead are extended through the first groove and the second groove, respectively, and a heat dissipation part is extended from the first lead through the third groove to an outside of the LED package.

Abstract: A photodiode array 1 has a plurality of photodetector channels 10 which are formed on an n-type substrate 2 having an n-type semiconductor layer 12, with a light to be detected being incident to the plurality of photodetector channels 10. The photodiode array 1 comprises: a p?-type semiconductor layer 13 formed on the n-type semiconductor layer 12 of the substrate 2; resistors 4 each of which is provided to each of the photodetector channels 10 and is connected to a signal conductor 3 at one end thereof; and an n-type separating part 20 formed between the plurality of photodetector channels 10. The p?-type semiconductor layer 13 forms a pn junction at the interface between the substrate 2, and comprises a plurality of multiplication regions AM for avalanche multiplication of carriers produced by the incidence of the light to be detected so that each of the multiplication regions corresponds to each of the photodetector channels.

Abstract: A solid-state imaging device in which the potential of a signal line, which is obtained before a pixel has an operating period, is fixed to an intermediate potential between a first power-supply potential and a second power-supply potential.

Abstract: A surface between gate electrodes in an MOS gate structure is patterned so that missing portions are partially provided in surfaces of n+ emitter regions to thereby enlarge surface areas of p+ contact regions surrounded by the surfaces of the n+ emitter regions. In this manner, a highly reliable MOS type semiconductor device is provided which is improved in breakdown tolerance by suppressing an increase in the gain of a parasitic transistor caused by photo pattern defects produced easily in accordance with minute patterning in a process design rule.

Abstract: In accordance with some embodiments, logical circuits comprising carbon nanotube field effect transistors are disclosed herein.

Abstract: To provide a semiconductor device having a memory element, and which is manufactured by a simplified manufacturing process. A method of manufacturing a semiconductor device includes, forming a first insulating film to cover a first semiconductor film and a second semiconductor film; forming a first conductive film and a second conductive film over the first semiconductor film and the second semiconductor film, respectively, with the first insulating film interposed therebetween; forming a second insulating film to cover the first conductive film; forming a third conductive film selectively over the first conductive film which is formed over the first semiconductor film, with the second insulating film interposed therebetween, and doping the first semiconductor film with an impurity element with the third conductive film serving as a mask and doping the second semiconductor film with the impurity element through the second conductive film.

Abstract: According to an aspect of the present invention, there is provided a semiconductor device including: a substrate that includes a semiconductor region including Ge as a primary component; a compound layer that is formed above the semiconductor region, that includes Ge and that has a non-metallic characteristic; an insulator film that is formed above the compound layer; an electrode that is formed above the insulator film; and source/drain regions that is formed in the substrate so as to sandwich the electrode therebetween.

Abstract: A semiconductor device includes: a semiconductor substrate having first and second areas; an STI isolation region being made of an isolation trench formed in the semiconductor substrate and an insulating film burying the isolation trench and defining a plurality of active regions in the first and second areas; a first structure formed on an area from the active region in the first area to a nearby STI isolation region and having a first height; and a second structure formed on an area from the active region in the second area to a nearby STI isolation region and having a second height, wherein the surface of the said STI isolation region in the first area is lower than the surface of said STI isolation region in the second area.