Abstract: The invention concerns a device for detecting and storing electromagnetic beams, an imager incorporating same, a method for making said device and use thereof. The inventive device comprises a field-effect phototransistor including: two source and drain contact electrodes, an electrical conduction unit which is connected to the two contact electrodes and which is coated with a photosensitive polymeric coating capable of absorbing the beams, of detecting, of generating in response the loads detected by said unit and of storing said loads, and a gate electrode which is capable of controlling the electric current in the unit as well as spatially distributing the loads in said coating and which is separated from said unit by a gate dielectric.

Abstract: The present invention discloses a suspended nanochannel transistor structure and a method for fabricating the same. The transistor structure of the present invention comprises a substrate; a side gate formed on the substrate; a dielectric layer covering the substrate and the side gate; a suspended nanochannel formed beside the lateral of the side gate with an air gap existing between the suspended nanochannel and the dielectric layer; a source and a drain formed over the dielectric layer and respectively arranged at two ends of the suspended nanochannel. The electrostatic force of the side gate attracts or repels the suspended nanochannel and thus fast varies the equivalent thickness of the side-gate dielectric layer. Thereby, the on/off state of the element is rapidly switched, or the initial voltage of the channel is altered.

Abstract: Integrated circuit packages incorporating an inductor and methods for their fabrication. The lead frame used in packaging the integrated circuit includes a first area for receiving the integrated circuit, and a second area having a plurality of connections from one side to the other side of the lead frame, thereby forming coil segments. After mounting the integrated circuit and wire bonding its connections, the lead frame is placed on a ferrite plate, the assembly is encapsulated in resin, and the leads trimmed and bent. Mounting of the packaged integrated circuit on a properly prepared printed circuit interconnects the coil segments in the package to coil segments on the printed circuit, thereby forming a single, multi-turn coil around the ferrite plate. Various embodiments are disclosed.

Abstract: Low voltage, middle voltage and high voltage CMOS devices have upper buffer layers of the same conductivity type as the sources and drains that extend under the sources and drains and the gates but not past the middle of the gates, and lower bulk buffer layers of the opposite conductivity type to the upper buffer layers extend from under the upper buffer layers to past the middle of the gates forming an overlap of the two bulk buffer layers under the gates. The upper buffer layers and the lower bulk buffer layers can be implanted for both the NMOS and PMOS FETs using two masking layers. For middle voltage and high voltage devices the upper buffer layers together with the lower bulk buffer layers provide a resurf region.

Abstract: A memory cell includes a semiconductor substrate; and a first, a second, and a third transistor. The first transistor includes a first dielectric over the semiconductor substrate; and a first floating gate over the first dielectric. The second transistor is electrically coupled to the first transistor and includes a second dielectric over the semiconductor substrate; and a second floating gate over the second dielectric. The first and the second floating gates are electrically disconnected. The memory cell further includes a first capacitor; a second capacitor electrically coupled to the first capacitor; a third capacitor; a fourth capacitor electrically coupled to the third capacitor, wherein each of the first, the second, the third and the fourth capacitors includes the semiconductor substrate as one of the capacitor plates. The third transistor is a selector of the memory cell and is electrically coupled to the first and the second transistors.

Abstract: The present invention relates to a flash memory cell string. The flash memory cell string includes a plurality of cell devices and switching devices connected to ends of the cell devices. Each of the cell devices includes a semiconductor substrate, and a transmissive insulating layer, a charge storage node, a control insulating layer and a control electrode sequentially formed on the semiconductor substrate. In the flash memory cell string, a buried insulating layer is provided on the semiconductor substrate between the cell device and an adjacent cell device, thus enabling an inversion layer, which performs the functions of source/drain, to be easily formed. According to the present invention, the reduction characteristics and performance of the cell devices of NAND flash memory are improved, and the inversion layer of a channel is induced through fringing electric fields from the control electrode and the charge storage node if necessary.

Abstract: A light emitting device includes a light emitting diode chip, a heat conductive plate mounting thereon the light emitting diode chip, a sub-mount member disposed between said light emitting diode chip and said heat conductive plate, a dielectric substrate stacked on the heat conductive plate and being formed with a through-hole through which the sub-mount member is exposed, an encapsulation member for encapsulation of said light emitting diode chip, and a lens superimposed on the encapsulation member. The sub-mount member is formed around a coupling portion of the light emitting diode chip with a reflective film which reflects a light emitted from a side face of the light emitting diode chip. The sub-mount member is selected to have a thickness such that the reflecting film has its surface spaced away from said heat conductive plate by a greater distance than said dielectric substrate.

Abstract: A first P channel transistor and a first N channel transistor are defined by first and second gate electrodes, respectively. The second gate electrode is electrically connected to the first gate electrode. A second P channel transistor and a second N channel transistor are defined by third and fourth gate electrodes, respectively. The fourth gate electrode is electrically connected to the third gate electrode. Each of the first P channel transistor, first N channel transistor, second P channel transistor, and second N channel transistor has a respective diffusion terminal electrically connected to a common node. Each of the first, second, third, and fourth gate electrodes is defined to extend along any of a number of parallel oriented gate electrode tracks without physically contacting a gate level feature defined within any gate level feature layout channel associated with a gate electrode track adjacent thereto.

Abstract: A dual-bit memory device is provided which includes trench isolation material disposed near bit line contact areas. For example, in one implementation a semiconductor memory device is provided in which each memory cell can store two bits of information. The memory device comprises a substrate, first and second buried bit lines in the substrate, a first bit line contact on the first buried bit line, a second bit line contact on the second buried bit line, and an insulator region disposed in the substrate between the first buried bit line and the second buried bit line. The insulator region prevents a current from flowing between the first buried bit line and the second buried bit line.

Abstract: Optimizing carrier mobilities in MOS transistors in CMOS ICs requires forming (100)-oriented silicon regions for NMOS and (110) regions for PMOS. Boundary regions between (100) and (110) regions must be sufficiently narrow to support high gate densities and SRAM cells appropriate for the technology node. This invention provides a method of forming an integrated circuit (IC) substrate containing regions with two different silicon crystal lattice orientations. Starting with a (110) direct silicon bonded (DSB) layer on a (100) substrate, regions in the DSB layer are amorphized and recrystallized on a (100) orientation by solid phase epitaxy (SPE). Lateral templating by the DSB layer is reduced by amorphization of the upper portion of the (110) regions through a partially absorbing amorphization hard mask. Boundary morphology is less than 40 nanometers wide. An integrated circuit formed with the inventive method is also disclosed.

Abstract: A unit cell of a metal-semiconductor field-effect transistor (MESFET) is provided. The MESFET has a source, a drain and a gate. The gate is between the source and the drain and on an n-type conductivity channel layer. A p-type conductivity region is provided beneath the gate between the source and the drain. The p-type conductivity region is spaced apart from the n-type conductivity channel layer and electrically coupled to the gate. Related methods are also provided herein.

Abstract: A nonvolatile semiconductor memory apparatus includes: a memory element including: a semiconductor substrate; a source region and a drain region formed at a distance from each other in the semiconductor substrate; a first insulating film formed on a portion of the semiconductor substrate located between the source region and the drain region, having sites that perform electron trapping and releasing and are formed by adding an element different from a base material, and including insulating layers having different dielectric constants, the sites having a higher level than a Fermi level of a material forming the semiconductor substrate; a charge storage film formed on the first insulating film; a second insulating film formed on the charge storage film; and a control gate electrode formed on the second insulating film.

Abstract: A pixel for a CMOS photo sensor with increased full well capacity is disclosed. The pixel having a photosensitive element, a photo gate, potential well and a readout circuit. The photosensitive element having a front side and a back side, for releasing charge when light strikes the back side of the photosensitive element. The potential well receives the released charge from the photosensitive element. The photo gate located on the front side of the photosensitive element, for transferring the released charge from the potential well to a sense node. The readout circuit coupled to the sense node, for measuring a voltage corresponding to the released charge transferred to the sense node.

Abstract: Disclosed is a method of manufacturing an organic light emitting device, an organic light emitting device manufactured by using the method, and an electronic device including the organic light emitting device. The method includes (a) forming an insulating layer on a lower electrode, (b) etching the insulating layer to form an opening ranging from an upper surface of the insulating layer to the lower electrode so that an overhang structure having a lowermost circumference that is larger than an uppermost circumference is formed, (c) forming a conductive layer on an upper surface of the lower electrode in the opening and a surface of the insulating layer other than the overhang structure, (d) forming an organic material layer on the conductive layer formed on the upper surface of the lower electrode in the opening, and (e) forming an upper electrode on an upper surface of the conductive layer disposed on the upper surface of the insulating layer and an upper surface of the organic material layer.

Abstract: A low on-resistance silicon carbide semiconductor device is provided to include an ohmic electrode of low contact resistance and high adhesion strength formed on a lower surface of silicon carbide. Specifically, the silicon carbide semiconductor device includes at least an insulating film, formed on an upper surface of a silicon carbide substrate, and includes at least an ohmic electrode, formed of an alloy comprising nickel and titanium, or formed of a silicide comprising nickel and titanium, and which is formed on the lower surface of the silicon carbide substrate.

Abstract: A single crystal semiconductor layer of a first conduction type is disposed on a surface of a semiconductor substrate. A plurality of trenches are provided in the semiconductor layer to form a plurality of first semiconductor regions of the first conduction type at intervals in a direction parallel to the surface. An epitaxial layer is buried in the plurality of trenches to form a plurality of second semiconductor regions of a second conduction type. The plurality of second semiconductor regions each includes an outer portion with a high impurity concentration formed against an inner wall of the trench, and an inner portion with a low impurity concentration formed inner than the outer portion.

Abstract: In a laser chip 1 using a nitride semiconductor having a hexagonal crystal structure, the ?c plane is used as a first resonator facet A, which is the side of the laser chip 1 through which light is emitted. On the first resonator facet A, that is, on the ?c plane, a facet protection film 14 is formed. This ensures firm joint between the first resonator facet A and the facet protection film 14 and alleviates deterioration of the first resonator facet A.

Abstract: A semiconductor device which may include a semiconductor layer, and a superlattice interface layer therebetween. The superlattice interface layer may include a plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. At least some atoms from opposing base semiconductor portions may be chemically bound together with the chemical bonds traversing the at least one intervening non-semiconductor monolayer.

Abstract: As well as achieving both downsizing and thickness reduction and sensitivity improvement of a semiconductor device that has: a MEMS sensor formed by bulk micromachining technique such as an acceleration sensor and an angular rate sensor; and an LSI circuit, a packaging structure of the semiconductor device having the MEMS sensor and the LSI circuit can be simplified. An integrated circuit having MISFETs and wirings is formed on a silicon layer of an SOI substrate, and the MEMS sensor containing a structure inside is formed by processing a substrate layer of the SOI substrate. In other words, by using both surfaces of the SOI substrate, the integrated circuit and the MEMS sensor are mounted on one SOI substrate. The integrated circuit and the MEMS sensor are electrically connected to each other by a through-electrode provided in the SOI substrate.

Abstract: A stacked die chip scale package, in which a stacked die assembly is mounted within a cavity in a module substrate. In some embodiments certain of the die are stacked on a front side of a stacked die assembly substrate, and the stacked die assembly substrate is inverted in the cavity and the substrate is electrically interconnected to a front side of the module substrate; others of the die are stacked on the back side of the stacked die assembly substrate, and are interconnected by wire bonds to the front side of the module substrate. In some embodiments, the cavity is covered by a heat sink, and the stacked die assembly is mounted onto the heat sink. Also, methods for making the module are provided.