Patents Examined by Wael Fahmy
  • Patent number: 10217739
    Abstract: A bipolar junction transistor having a relatively reduced size and an improved current gain and a method of manufacturing the same are disclosed. The bipolar junction transistor includes a plurality of emitter regions disposed in a substrate, a plurality of base regions disposed in the substrate and configured to surround the emitter regions, respectively, and a collector region disposed in the substrate and configured to surround the base regions. The plurality of emitter and base regions may be arranged in a matrix.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: February 26, 2019
    Assignee: DB Hitek Co., Ltd
    Inventor: Joo Hyung Kim
  • Patent number: 10211242
    Abstract: An image sensor is provided. The image sensor includes a visible light receiving portion and an infrared receiving portion. The visible light receiving portion is configured to receive a visible light. The infrared receiving portion is configured to receive infrared. The visible light receiving portion comprises an infrared cutoff filter, plural primary color filters, and plural secondary color filters. The primary color filters and the secondary color filters are disposed on the infrared cutoff filter. The infrared receiving portion comprises plural first infrared pass filters and plural second infrared pass filters disposed on the first infrared pass filters. Each of the primary color filters occupies a first area. The secondary color filters and the second infrared pass filters occupy a second area substantially equal to the first area.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: February 19, 2019
    Assignee: HIMAX TECHNOLOGIES LIMITED
    Inventors: Yu-Jui Hsieh, Po-Nan Chen
  • Patent number: 10164003
    Abstract: A method of forming a metal-insulator-metal capacitor is provided. The method includes forming a first metal plate over a semiconductor substrate, forming a first dielectric layer with a first dielectric constant on a surface of the first metal plate, forming a second dielectric layer with a second dielectric constant on a surface of the first dielectric layer, forming a third dielectric layer with a third dielectric constant on a surface of the second dielectric layer, and forming a second metal plate on a surface of the third dielectric layer. The second dielectric constant is different from the first dielectric constant and different from the third dielectric constant.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hsing-Lien Lin, Hai-Dang Trinh, Cheng-Yuan Tsai
  • Patent number: 10164177
    Abstract: A magnetic junction usable in a magnetic device and a method for providing the magnetic junction are described. A first portion of a magnetoresistive stack corresponding to the magnetic junction is provided. Providing this portion of the magnetoresistive stack includes providing at least one layer for a free layer of the magnetic junction. A second portion of the magnetoresistive stack is provided after the step of providing the first portion of the magnetoresistive stack. The magnetoresistive stack is patterned to provide the magnetic junction after the step of providing the second portion of the magnetoresistive stack. An ambient temperature for the magnetoresistive stack and the magnetic junction does not exceed a crystallization temperature of the free layer after the step of providing the free layer through the step of patterning the magnetoresistive stack.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: December 25, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sebastian Schafer, Dmytro Apalkov, Vladimir Nikitin, Don Koun Lee
  • Patent number: 10090194
    Abstract: A method of manufacturing a semiconductor device includes the step of positioning a patterned mask over a dielectric layer. The dielectric layer comprises a low-temperature cure polyimide. The method further includes the steps of exposing a first surface of the dielectric layer through the patterned mask to an I-line wavelength within an I-line stepper, and developing the dielectric layer to form an opening.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: October 2, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zi-Jheng Liu, Yu-Hsiang Hu, Hung-Jui Kuo
  • Patent number: 9761718
    Abstract: A semiconductor device includes: a sidewall insulating film; a gate electrode; source and drain regions; a first stress film; and a second stress film.
    Type: Grant
    Filed: February 20, 2009
    Date of Patent: September 12, 2017
    Assignee: SONY CORPORATION
    Inventor: Yuki Miyanami
  • Patent number: 9721974
    Abstract: The present invention relates to an array substrate, a method for manufacturing the same and a display device. The array substrate comprises a substrate, and a first region and a second region that are provided on the substrate and adjacent to each other and a difference in level between the two exceeds a threshold, a difference-in-level compensation pattern is provided on the substrate, which overlaps with both the first region and the second region in a direction perpendicular to the substrate and does not exceed the first region and the second region. By the technical solution of the present invention, the difference in level between the data line and an adjacent region on the array substrate is reduced, so that during a rubbing process, the rubbing area of a polyimide solution is increased, and the risk of light leakage is reduced without a decrease of the pixel aperture ratio.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: August 1, 2017
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Shan Gao
  • Patent number: 9508425
    Abstract: A non-volatile memory device structure. The non-volatile memory device structure comprises a first electrode formed from a first metal material, a resistive switching element overlying the first electrode. The resistive switching element comprises a metal oxide material characterized by one or more oxygen deficient sites. The device includes a second electrode overlying the resistive switching layer, the second electrode being formed from a second metal material. The second electrode is made from a noble metal. The one or more oxygen deficient sites are caused to migrate from one of the first electrode or the second electrode towards the other electrode upon a voltage applied to the first electrode or the second electrode. The device can have a continuous change in resistance upon applying a continuous voltage ramp, suitable for an analog device. Alternatively, the device can have a sharp change in resistance upon applying the continuous voltage ramp, suitable for a digital device.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: November 29, 2016
    Assignee: THE REGENTS OF THE UNIVERSITY OF MICHIGAN
    Inventors: Wei Lu, Sung Hyun Jo
  • Patent number: 9508797
    Abstract: A semiconductor device in provided having a substrate and a semiconductor layer formed on a main surface of the substrate. A plurality of first island electrodes and a plurality of second island electrodes are placed over the semiconductor layer. The plurality of first island electrodes and second island electrodes are spaced apart from each other so as to be alternatively arranged to produce two-dimensional active regions in all feasible areas of the semiconductor layer. Each side of the first island electrodes is opposite a side of the second island electrodes. The semiconductor device can also include a plurality of strip electrodes that are formed in the regions between the first island electrodes and the second island electrodes. The strip electrodes serve as the gate electrodes of a multi-island transistor. The first island electrodes serve as the source electrodes of the multi-island transistor. The second island electrodes serve as the drain electrodes of the multi-island transistor.
    Type: Grant
    Filed: April 8, 2015
    Date of Patent: November 29, 2016
    Assignee: GAN SYSTEMS INC.
    Inventors: John Roberts, Ahmad Mizan, Girvan Patterson, Greg Klowak
  • Patent number: 9484297
    Abstract: Integrated circuits with single core inductors and methods for producing them are provided. Embodiments include forming a trench in a dielectric layer; forming a first metal-oxide hard mask by disposing a metal hard mask and an oxide hard mask over the dielectric layer and in strips in the trench; forming metal line trenches through the first metal-oxide hard mask and into the first dielectric layer on opposite sides of the inductor trench and first vias; filling the first metal line trenches, first vias, and trench; forming another dielectric layer and a second metal-oxide hard mask over the filled trench; forming a second trench through the second metal-oxide hard mask and into the second dielectric layer and second metal line trenches and second vias; and filling the second metal line trenches, second vias, and second trench.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: November 1, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ki Young Lee, Moosung M. Chae, Woo Sik Kim
  • Patent number: 9478441
    Abstract: An improved superjunction semiconductor device includes a charged balanced pylon in a body region, where a top of the pylon is large to create slight charge imbalance. A MOSgated structure is formed over the top of the pylon and designed to conduct current through the pylon. By increasing a dimension of the top of the pylon, the resulting device is less susceptible to variations in manufacturing tolerances to obtain a good breakdown voltage and improved device ruggedness.
    Type: Grant
    Filed: August 3, 2010
    Date of Patent: October 25, 2016
    Assignee: SILICONIX TECHNOLOGY C. V.
    Inventor: Srikant Sridevan
  • Patent number: 9465154
    Abstract: To provide a light emitting device that makes it possible to form a surface light emitting apparatus of less unevenness in luminance. The light emitting device 10 of the present invention comprises a light emitting element 30, connecting terminals 21a, 21b connected with the light emitting element 30, a package 12 which has a recess 40 wherein the light emitting element 30 is mounted and from which a part of each connecting terminal 21a, 21b is projected outward, an opening 41 of the recess 40 being elongated in one direction, wherein both side walls of the recess 40 positioned in the longitudinal direction of the recess 40 are inclined surface 43, an angle ? between both the inclined surfaces 43 being 90 degrees or more. In the light emitting device 10 of the present invention, light emitted by the light emitting element 30 is spread sufficiently in the longitudinal direction of the opening 41 so as to produce a band-shaped beam.
    Type: Grant
    Filed: May 13, 2014
    Date of Patent: October 11, 2016
    Assignee: NICHIA CORPORATION
    Inventors: Tomoaki Kashiwao, Takeo Kurimoto
  • Patent number: 9455240
    Abstract: Reliability of a semiconductor device is improved. Each of a plurality of terminals formed on a chip mounting surface included in a wiring substrate has a shape in which a narrow width portion is arranged between adjacent wide width portions in plan view. Moreover, a center of a tip end surface of each of a plurality of protruding electrodes formed on a semiconductor chip mounted on the wiring substrate is arranged at a position where it overlaps the narrow width portion in plan view, and the plurality of terminals and the plurality of protruding electrodes are electrically connected to each other via a solder member.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: September 27, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Jumpei Konno, Takafumi Nishita, Nobuhiro Kinoshita, Kazunori Hasegawa, Michiaki Sugiyama
  • Patent number: 9431497
    Abstract: Transistor devices having an anti-fuse configuration and methods of forming the transistor devices are provided. An exemplary transistor device includes a semiconductor substrate including a first fin. A first insulator layer overlies the semiconductor substrate and has a thickness less than a height of the first fin. The first fin extends through and protrudes beyond the first insulator layer to provide a buried fin portion and an exposed fin portion. A gate electrode structure overlies the exposed fin portion. A gate insulating structure is disposed between the first fin and the gate electrode structure. The gate insulating structure includes a first dielectric layer overlying a first surface of the first fin. The gate insulating structure further includes a second dielectric layer overlying a second surface of the first fin. A potential breakdown path is defined between the first fin and the gate electrode structure through the first dielectric layer.
    Type: Grant
    Filed: May 21, 2013
    Date of Patent: August 30, 2016
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Eng Huat Toh, Shyue Seng Tan, Elgin Quek
  • Patent number: 9419131
    Abstract: A semiconductor device having a substrate; a plurality of pillar structures, wherein each pillar structure includes an active pillar disposed over the substrate; a gate electrode surrounding an outer wall of the active pillar; an interlayer dielectric (ILD) layer insulating adjacent pillar structures; a gate contact penetrating the ILD layer and configured to connect to a sidewall of the gate electrode; and a word line connected to the gate contact.
    Type: Grant
    Filed: May 22, 2014
    Date of Patent: August 16, 2016
    Assignee: SK HYNIX INC.
    Inventors: Min-Gyu Sung, Yong-Soo Kim, Kwan-Yong Lim
  • Patent number: 9391262
    Abstract: Described are Spin Hall Magnetic Random Access Memory (MRAM) cells and arrays. In one embodiment, an apparatus includes a nanomagnet having a cross-sectional area and a spin Hall effect (SHE) material. The SHE material is coupled to a subset of the cross-sectional area of the nanomagnet.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: July 12, 2016
    Assignee: Intel Corporation
    Inventors: Dmitri E. Nikonov, Sasikanth Manipatruni, Ian A Young
  • Patent number: 9390997
    Abstract: The disclosure relates to a semiconductor chip and a stacked type semiconductor package having the same. The semiconductor chip includes: a semiconductor chip body having a first surface formed with a plurality of bonding pads and a second surface which is opposite to the first surface, a plurality of first and second through electrodes that pass through the semiconductor chip body and one ends thereof are electrically connected to the bonding pads, an insulating layer formed over the second surface of the semiconductor chip body such that the other ends of the first and second through electrodes are not covered by the insulating layer, and a first heat spreading layer formed over the insulating layer.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: July 12, 2016
    Assignee: SK hynix, Inc.
    Inventors: Jong Hoon Kim, Jae Hyun Son, Byoung Do Lee, Kuk Jin Chun, Woong Kyu Choi
  • Patent number: 9385055
    Abstract: A method of assembling a semiconductor chip device is provided that includes placing an interposer on a first semiconductor chip. The interposer includes a first surface seated on the first semiconductor chip and a second surface adapted to thermally contact a heat spreader. The second surface includes a first aperture. A second semiconductor chip is placed in the first aperture.
    Type: Grant
    Filed: August 20, 2010
    Date of Patent: July 5, 2016
    Assignees: ATI Technologies ULC, Advanced Micro Devices, Inc.
    Inventors: Gamal Refai-Ahmed, Michael Z. Su, Bryan Black, Maxat Touzelbaev, Yizhang Yang
  • Patent number: 9368454
    Abstract: A semiconductor device includes a semiconductor substrate, a dielectric layer, a passivation layer, a protective layer, a post-passivation interconnect (PPI) structure, and a shielding layer. The semiconductor substrate has electrical circuitry. The dielectric layer is formed on the semiconductor substrate. The passivation layer is formed on the dielectric layer. The first protective layer is formed on the passivation layer. The PPI structure is disposed on the first protective layer and has a signal line and a ground line. The shielding layer is disposed over the semiconductor substrate and between the signal line and the electrical circuitry. The shielding layer is substantially equi-potentially connected to the ground line of the PPI structure.
    Type: Grant
    Filed: October 10, 2013
    Date of Patent: June 14, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Hao Tsai, Wei-Chih Lai, Chuei-Tang Wang, Chen-Hua Yu
  • Patent number: 9368580
    Abstract: A solution for designing and/or fabricating a structure including a quantum well and an adjacent barrier is provided. A target band discontinuity between the quantum well and the adjacent barrier is selected to coincide with an activation energy of a dopant for the quantum well and/or barrier. For example, a target valence band discontinuity can be selected such that a dopant energy level of a dopant in the adjacent barrier coincides with a valence energy band edge for the quantum well and/or a ground state energy for free carriers in a valence energy band for the quantum well. Additionally, a target doping level for the quantum well and/or adjacent barrier can be selected to facilitate a real space transfer of holes across the barrier. The quantum well and the adjacent barrier can be formed such that the actual band discontinuity and/or actual doping level(s) correspond to the relevant target(s).
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: June 14, 2016
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Maxim S. Shatalov, Remigijus Gaska, Jinwei Yang, Michael Shur