Abstract: A method for forming optical devices. The method includes providing a gallium nitride substrate member having a crystalline surface region and a backside region. The method also includes subjecting the backside region to a laser scribing process to form a plurality of scribe regions on the backside region and forming a metallization material overlying the backside region including the plurality of scribe regions. The method removes at least one optical device using at least one of the scribe regions.

Abstract: A semiconductor device includes a supplementary layer and a silicon layer stacked over a substrate, a trench penetrating the supplementary layer and the silicon layer and formed over the substrate, a gate insulation layer formed along a surface of the trench, and a buried gate formed over the gate insulation layer and filling a portion of the trench.

Abstract: When forming a super junction by the embedded epitaxial method, adjusting a taper angle of dry etching to form an inclined column is generally performed in trench forming etching, in order to prevent a reduction in breakdown voltage due to fluctuations in concentration in an embedded epitaxial layer. However, according to the examination by the present inventors, it has been made clear that such a method makes design more and more difficult in response to the higher breakdown voltage. In the present invention, the concentration in an intermediate substrate epitaxy column area in each substrate epitaxy column area configuring a super junction is made more than that in other areas within the substrate epitaxy column area, in a vertical power MOSFET having the super junction by the embedded epitaxial method.

Abstract: The present invention provides a single-sided access device including an active fin structure comprising a source region and a drain region; an insulating layer interposed between the source region and the drain region; a trench isolation structure disposed at one side of the active fin structure; a single-sided sidewall gate electrode disposed on the other side of the active fin structure opposite to the trench isolation structure so that the active fin structure is sandwiched by trench isolation structure and the single-sided sidewall gate electrode; and a gate protrusion laterally and electrically extended from the single-sided sidewall gate electrode and embedded between the source region and the drain region under the insulating layer.

Abstract: A semiconductor device in provided having a substrate and a semiconductor layer formed on a main surface of the substrate. A plurality of first island electrodes and a plurality of second island electrodes are placed over the semiconductor layer. The plurality of first island electrodes and second island electrodes are spaced apart from each other so as to be alternatively arranged to produce two-dimensional active regions in all feasible areas of the semiconductor layer. Each side of the first island electrodes is opposite a side of the second island electrodes. The semiconductor device can also include a plurality of strip electrodes that are formed in the regions between the first island electrodes and the second island electrodes. The strip electrodes serve as the gate electrodes of a multi-island transistor. The first island electrodes serve as the source electrodes of the multi-island transistor. The second island electrodes serve as the drain electrodes of the multi-island transistor.

Abstract: This invention comprises a method to make small MTJ element using hybrid etching and oxygen plasma immersion ion implantation. The method has no removal of the magnetic free layer (or memory layer) and hence prevents any possible physical damage near the free layer edges. After photolithography patterning, alternative Ta, Ru, Ta etchings are performed before it stops on an MgO intermediate layer above the free layer. Then an oxygen plasma immersion ion implantation is performed to completely oxidize the exposed portion of the free layer, leaving the hard mask covered portion unchanged which define the lateral width of the MTJ element.

Abstract: A method of making an optoelectronic system in accordance with the present disclosure is disclosed. The method includes providing a temporary substrate; providing un-packaged optoelectronic elements having sidewalls, top surfaces, and bottom surfaces, at least one of the unpackaged optoelectronic elements having an electrode provided on a side of the bottom surfaces; attaching the bottom surfaces to the temporary substrate such that a trench is formed between two of the un-packaged optoelectronic elements; providing an adhesive material to fully fill the trench and cover the un-packaged optoelectronic elements such that the sidewalls and top surfaces of the un-packaged optoelectronic elements are fully enclosed by the adhesive material; providing a transparent substrate on the adhesive material; and removing the temporary substrate without removing all the adhesive material covering the optoelectronic elements.

Abstract: A method of transferring a uniform phosphor layer on an article and a light-emitting structure having a uniform phosphor layer. The method includes disposing a surface of the article in a proximity of a carrier having the uniform phosphor layer on a surface thereon, and causing the uniform phosphor layer to be secured to the surface of the article. Therefore, the uniform phosphor layer is secured to the articles according to a contour of the article.

Abstract: A structure of a light emitting diode is provided. In one aspect, a light emitting diode structure comprises a light emitting diode, a conductive frame, and a substrate. The conductive frame is electrically connected to the light emitting diode and has a fixing hole connecting a first side of the conductive frame and a second side of the conductive frame opposite the first side. The fixing hole has a ladder-shaped inner sidewall with a first radius of the inner sidewall adjacent the first side smaller than a second radius of the inner sidewall adjacent the second side. The substrate has a conductive pillar that is received in the fixing hole by entering the fixing hole from the first side of the conductive frame and deformed such that the conductive pillar adheres to the ladder-shaped inner sidewall of the fixing hole.

Abstract: Provided are a light emitting device and a method of manufacturing the same. The light emitting device includes each of first and second semiconductor stacked structures including first and second conductive type semiconductor layers and an active layer, first and second contacts on tops and bottoms of the first and second semiconductor stacked structures to be connected to the first and second conductive type semiconductor layers, a substrate structure including first and second sides, a first insulation layer on an area where no second contact is formed among a surface of the first and second semiconductor stacked layers, first and second conductive layers connected to the second contacts of the first and second semiconductor stacked structures, first and second wiring layers on the first side of the substrate structure, and first and second external connection terminals connected to the first and second contacts of the first semiconductor stacked structure.

Abstract: A semiconductor structure with beryllium oxide is provided. The semiconductor structure comprises: a semiconductor substrate (100); and a plurality of insulation oxide layers (201, 202 . . . 20x) and a plurality of single crystal semiconductor layers (301, 302 . . . 30x) alternately stacked on the semiconductor substrate (100). A material of the insulation oxide layer (201) contacted with the semiconductor substrate (100) is any one of beryllium oxide, SiO2, SiOxNy and a combination thereof, a material of other insulation oxide layers (202 . . . 20x) is single crystal beryllium oxide.

Abstract: The present invention discloses to a method of depositing the metal barrier layer comprising silicon dioxide. It is applied in the transistor device comprising a silicon substrate, a gate and a gate side wall. The method comprises the following steps: ions are implanted into the silicon substrate to form an active region in the said silicon substrate; a first dense silicon dioxide film is deposited; a second normal silicon dioxide film is deposited; the said transistor device is high temperature annealed. The present invention ensures that the implanted ion is not separated out of the substrate during the annealing. And it prevents the warping and fragment of the silicon surface.

Abstract: A thin film transistor (TFT) array substrate with few processing steps and simple structure is provided, wherein merely two patterned metal layers are required and a patterned planarization layer is adopted to separate the two patterned metal layers from each other and thereby reduce power loading. In addition, the patterned planarization layer has slots to form height differences so as to separate scan lines from common electrodes to further reduce the power loading.

Abstract: An improved electrical-fuse (e-fuse) device including a dielectric layer having a first top surface, two conductive features embedded in the dielectric layer and a fuse element. Each conductive feature has a second top surface and a metal cap directly on the second top surface. Each metal cap has a third top surface that is above the first top surface of the dielectric layer. The fuse element is on the third top surface of each metal cap and on the first top surface of the dielectric layer. A method of forming the e-fuse device is also provided.

Abstract: A semiconductor device having Cu wiring including a basic crystal structure which can reduce surface voids, and an inspecting technique for the semiconductor device. In the semiconductor device, surface voids can be reduced down to 1/10 or less of a current practical level by specifying a barrier layer and a seed layer and setting a proportion (frequency) of occupation of a coincidence site lattice (CSL) boundary having a grain boundary Sigma value 27 or less to all crystal grain boundaries of a Cu wiring to 60% or higher. Alternatively, a similar effect of surface void reduction can be obtained by specifying a barrier layer and a seed layer and setting a proportion (frequency) of occupation of a coincidence site lattice (CSL) boundary having a grain boundary Sigma value 3 to all crystal grain boundaries of a Cu wiring to 40% or higher.

Abstract: Disclosed is an integrated circuit having an asymmetric FET as a power gate for an electronic circuit, which has at least two stacked symmetric field effect transistors. The asymmetric FET has an asymmetric halo configuration (i.e., a single source-side halo or a source-side halo with a higher dopant concentration than a drain-side halo) and an asymmetric source/drain extension configuration (i.e., the source extension can be overlapped to a greater extent by the gate structure than the drain extension and/or the source extension can have a higher dopant concentration than the drain extension). As a result, the asymmetric FET has a low off current. In operation, the asymmetric FET is turned off when the electronic circuit is placed in a standby state and, due to the low off current (Ioff), effectively reduces standby leakage current from the electronic circuit.

Abstract: An electrode for an energy storage device with less deterioration due to charge and discharge, and a method for manufacturing thereof are provided. Further, an energy storage device having large capacity and high endurance can be provided. In an electrode of an energy storage device in which an active material is formed over a current collector, the surface of the active material is formed of a crystalline semiconductor film having a {110} crystal plane. The crystalline semiconductor film having a {110} crystal plane may be a crystalline silicon film containing a metal element which reacts with silicon to form a silicide. Alternatively, the crystalline semiconductor film having a {110} crystal plane may be a crystalline semiconductor film containing silicon as its main component and also containing germanium and a metal element which reacts with silicon to form a silicide.

Abstract: An ordered multilayer crystalline organic thin film structure is formed by depositing at least two layers of thin film crystalline organic materials successively wherein the at least two thin film layers are selected to have their surface energies within ±50% of each other, and preferably within ±15% of each other, whereby every thin film layer within the multilayer crystalline organic thin film structure exhibit a quasi-epitaxial relationship with the adjacent crystalline organic thin film.

Abstract: A resistive random access memory cell uses a substrate and includes a gate stack over the substrate. The gate stack includes a first copper layer over the substrate, a copper oxide layer over the first copper layer, and a second copper layer over the copper oxide layer.

Abstract: Disclosed is an organic electroluminescence device which can be stably produced by a wet process and exhibits enhanced external quantum efficiency and reduced coating unevenness and a production method thereof. Specifically, disclosed is a method of producing the organic electroluminescence device comprising at least a layer, which is formed by a wet process comprising of coating a solution of an organic material dissolved in a solvent to form a liquid layer, followed by removal of the solvent by blowing air to form the layer, wherein the relative drying rate of the solvent to butyl acetate is from 1 to 1000, (based on the drying rate of butyl acetate being 100), the thickness of the formed liquid layer is from 1 to 100 ?m, a air-blowing rate is from 0.1 to 5 m/s and the time between completion of coating and start of blowing is from 0 to 60 sec.