Abstract: Some embodiments include memory cells which have multiple programmable material structures between a pair of electrodes. One of the programmable material structures has a first edge, and another of the programmable material structures has a second edge that contacts the first edge. Some embodiments include methods of forming an array of memory cells. First programmable material segments are formed over bottom electrodes. The first programmable material segments extend along a first axis. Lines of second programmable material are formed over the first programmable material segments, and are formed to extend along a second axis that intersects the first axis. The second programmable material lines have lower surfaces that contact upper surfaces of the first programmable material segments. Top electrode lines are formed over the second programmable material lines.

Abstract: Semiconductor devices having reduced parasitic current and methods of malting the semiconductor devices are provided. Further provided are memory devices having reduced adjacent wordline disturb. The memory devices contain wordlines formed over a semiconductor substrate, wherein at least one wordline space is formed between the wordlines. Adjacent wordline disturb is reduced by implanting one or more of indium, boron, and a combination of boron and indium in the surface of the at least one wordline space.

Abstract: A method of processing semiconductor dies is provided. Each semiconductor die has a first side with one or more terminals, a second side opposite the first side and sidewalls extending between the first and the second sides. The semiconductor dies are processed by placing the semiconductor dies on a support substrate so that the first side of each semiconductor die faces the support substrate and the second side faces away from the support substrate. A coating is applied to the semiconductor dies placed on the support substrate. The coating has a lower reflectivity than the first side of the semiconductor dies. The coating covers the second side and at least a region of the sidewalls nearest the second side of each semiconductor die. The semiconductor dies are removed from the support substrate after applying the coating for further processing as loose dies such as taping.

Abstract: Methods and apparatus are disclosed for the back end of line process for fabrication of integrated circuits (ICs). A barrier layer comprising a bottom part and a side part is formed within an opening for a metal contact, wherein the bottom part comprises a graphene material, the side part comprises an amorphous carbon material and covers a sidewall of the opening, and the bottom part and the side part are formed at a same time. A capping layer comprising a first part and a second part is formed on a dielectric layer and a metal contact, wherein the first part comprises a graphene material, the second part of the capping layer comprises an amorphous carbon material on the dielectric layer, and the first part and the second part are formed at a same time.

Abstract: Approaches for spacer chamfering in a replacement metal gate (RMG) device are provided. Specifically, a semiconductor device is provided with a set of fins formed from a substrate; a silicon-based layer conformally deposited over the set of fins; an etch-stop layer (e.g., titanium nitride (TiN)) formed over the silicon-based layer, the etch-stop layer being selective to at least one of: silicon, oxide, and nitride; a set of RMG structures formed over the substrate; a set of spacers formed along each of the set of RMG structures, wherein a vertical layer of material from each of the set of spacers is removed selective to the etch-stop layer. By chamfering each sidewall spacer, a wider area for subsequent work-function (WF) metal deposition is provided. Meanwhile, each transistor channel region is covered by the etch-stop layer (e.g., TiN), which maintains the original gate critical dimension during reactive ion etching.

Abstract: A back-illuminated silicon photodetector has a layer of Al2O3 deposited on a region of a silicon oxide surface that is left uncovered, while deposition is inhibited in another region by a contact shadow mask. The Al2O3 layer is an antireflection coating. In addition, the Al2O3 layer can also provide a chemically resistant separation layer between the silicon oxide surface and additional antireflection coating layers. In one embodiment, the silicon photodetector has a delta-doped layer near (within a few nanometers of) the silicon oxide surface. The Al2O3 layer is expected to provide similar antireflection properties and chemical protection for doped layers fabricated using other methods, such as MBE, ion implantation and CVD deposition.

Abstract: A semiconductor structure includes a substrate, an imaging pixel array disposed on a first region of the substrate, a first isolation disposed in the first region, a periphery circuitry disposed on a second region of the substrate, and a second isolation disposed in the second region. The imaging pixel array has a plurality of imaging pixels configured to capture image data. The periphery circuitry has a transistor configured to receive and process the image data. The first isolation has a first depth and a first protrusion projected from a surface of the substrate. The second isolation has a second depth and a second protrusion projected from the surface of the substrate. The first protrusion has a substantially same height as the second protrusion. The first depth is different from the second depth.

Abstract: A semiconductor structure includes a heterojunction bipolar transistor (HBT) including a collector layer located over a substrate, the collector layer including a semiconductor material, and a field effect transistor (FET) located over the substrate, the FET having a channel formed in the semiconductor material that forms the collector layer of the HBT. In some implementations, a second FET can be provided so as to be located over the substrate and configured to include a channel formed in a semiconductor material that forms an emitter of the HBT. One or more of the foregoing features can be implemented in devices such as a die, a packaged module, and a wireless device.

Abstract: A method for manufacturing a light-receiving device includes the steps of forming a stacked semiconductor layer including a non-doped light-receiving layer, the light-receiving layer having an n-type conductivity; forming a selective growth mask made of an insulating film on the stacked semiconductor layer, the selective growth mask having a pattern including a plurality of openings; selectively growing a selective growth layer doped with a p-type impurity on each portion of the stacked semiconductor layer by using the selective growth mask; and forming a p-n junction in each of plural regions of the light-receiving layer by diffusing the p-type impurity doped in each selective growth layer into the light-receiving layer during growing the selective growth layers. Each of the regions including one of the p-n junctions corresponds to one of the selective growth layers. The p-n junction in one of the regions is formed separately from the p-n junctions in the other regions.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor element, a mounting member including Cu, and a bonding layer provided between the semiconductor element and the mounting member. The bonding layer includes a first region including Ti and Cu, and a second region provided between the first region and the mounting member, and including Sn and Cu. A first position along the first direction is positioned between the semiconductor element and a second position along the first direction. The first position is where the composition ratio of Ti in the first region is 0.1 times a maximum value of the composition ratio of Ti. The second position is where the composition ratio of Sn in the second region is 0.1 times a maximum value of the composition ratio of Sn. A distance between the first position and the second position is not less than 0.1 micrometers.

Abstract: Embodiments of the invention provide an array substrate and a fabrication method thereof, and a liquid crystal display device. The array substrate comprises: a gate line, a data line, and a pixel unit formed by the gate line and the data line intersecting with each other. A first thin-film transistor and a pixel electrode are formed in the pixel unit, and the pixel electrode has slits. The pixel unit further comprises a second thin-film transistor, a first common electrode and a second common electrode, and the second thin-film transistor is configured to turn on and transmit a signal of the first common electrode to the second common electrode when a data line signal is at a high level.

Abstract: A dielectric material layer is formed on a semiconductor-on-insulator (SOI) substrate including a top semiconductor layer containing a first semiconductor material. An opening is formed within the dielectric material layer, and a trench is formed in the top semiconductor layer within the area of the opening by an etch. A second semiconductor material is deposited to a height above the top surface of the top semiconductor layer employing a selective epitaxy process. Another dielectric material layer can be deposited, and another trench can be formed in the top semiconductor layer. Another semiconductor material can be deposited to a different height employing another selective epitaxy process. The various semiconductor material portions can be patterned to form semiconductor fins having different heights and/or different compositions.

Abstract: A semiconductor device comprising: an active layer, which has a composition represented by the formula: AlxMyGa1-x-yN, wherein x satisfies 0?x?1, wherein y satisfies 0?y?1, wherein x+y satisfies 0?x+y?1, and wherein M contains at least one of In and B; a substrate containing GaN; and a buffer layer provided between the active layer and the substrate, wherein the semiconductor device is operated by electrical current flowing through the active layer in a direction parallel to a face of the substrate, wherein the buffer layer has a composition represented by the formula: AlpIn1-pN, wherein p satisfies 0?p<1, and wherein the buffer layer, which has a band gap energy wider than that of the substrate, and which is lattice-matched to the substrate.

Abstract: In an embodiment of the invention, a semiconductor device includes a first region having a first doping type, a channel region having the first doping type disposed in the first region, and a retrograde well having a second doping type. The second doping type is opposite to the first doping type. The retrograde well has a shallower layer with a first peak doping and a deeper layer with a second peak doping higher than the first peak doping. The device further includes a drain region having the second doping type over the retrograde well. An extended drain region is disposed in the retrograde well, and couples the channel region with the drain region. An isolation region is disposed between a gate overlap region of the extended drain region and the drain region. A length of the drain region is greater than a depth of the isolation region.

Abstract: The chip stack of semiconductor chips with enhanced cooling apparatus includes a first chip with circuitry on a first side and a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The chip stack further includes a thermal interface material pad between the first chip and the second chip. The thermal interface material pad comprises a plurality of nanotubes containing a magnetic material, aligned parallel to mating surfaces of the first chip and the second chip, wherein a hydrophobic tail of oleic acid is wrapped around each one of the plurality of nanotubes and a hydrophilic acid head of the oleic acid is attached to the magnetic material.

Abstract: A method for integrating a set of electronic devices on a wafer (100; 200a; 200b) of semiconductor material having a main surface includes forming a plurality of trenches extending into the wafer from the main surface. At least one layer of electrically insulating material is formed within each trench. At least one layer of electrically conductive material is formed within each trench superimposed on the at least one layer of insulating material. The formation of the plurality of trenches includes forming the trenches partitioned into sub-sets of trenches. The trenches of a first sub-set are oriented along a first common direction that is different from the orientation of the trenches of a second sub-set.

Abstract: A solid-state imaging device that includes at least one pixel. The pixel includes a photodiode, a floating diffusion element in a region of the photodiode and a read out gate electrode at least partially surrounding the floating diffusion element in plan view.

Abstract: An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, doped n-type throughout its length, and includes portions serving as gate electrodes of n-channel and p-channel MOS transistors; a plate of a metal-to-poly storage capacitor; and a plate of poly-to-active tunneling capacitors. The p-channel MOS transistor includes a buried channel region, formed by way of ion implantation, disposed between its source and drain regions. Silicide-block silicon dioxide blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit are silicide-clad.

Abstract: Semiconductor devices having non-merged fin extensions and methods for forming the same. Methods for forming semiconductor devices include forming fins on a substrate; forming a dummy gate over the fins, leaving a source and drain region exposed; etching the fins below a surface level of a surrounding insulator layer; and epitaxially growing fin extensions from the etched fins.

Abstract: At least one semiconductor fin is formed over an insulator layer. Portions of the insulator layer are etched from underneath the at least one semiconductor fin. The amount of the etched portions of the insulator is selected such that a metallic gate electrode layer fills the entire gap between the recessed surfaces of the insulator layer and the bottom surface(s) of the at least one semiconductor fin. An interface between the metallic gate electrode layer and a semiconductor gate electrode layer contiguously extends over the at least one semiconductor fin and does not underlie any of the at least one semiconductor fin. During patterning of a gate electrode, removal of the semiconductor material in the semiconductor gate electrode layer can be facilitated because the semiconductor gate electrode layer is not present under the at least one semiconductor fin.