Abstract: In an InAlAs/InGaAs heterojunction field type semiconductor device including an InP substrate, a superlattice layer formed by periods of InAs/AlAs or InAs/AlGaAs is formed over an InGaAs channel layer which is formed over the InP substrate.

Abstract: An output buffer in a CMOS circuit includes an output pad; a VDD line which supplies a first supply voltage; a VSS line which supplies a second supply voltage; a first MOS device connected between the VDD line and the output pad; a second MOS device connected between the VSS line and the output pad; a lateral SCR device connected from the output pad to one of the VDD and VSS lines and in parallel with one of the first and second MOS devices; and a bypass diode connected to one of the VDD and VSS lines and in parallel with the lateral SCR device.

Abstract: This invention discloses a heterojunction bipolar transistor (HBT) which includes a relatively thin intrinsic collector region and a relatively thick extrinsic collector region such that collector-base capacitance is reduced and electron transit time is maintained. The fabrication of the HBT includes loading a semi-insulating substrate into an molecular beam epitaxy machine, and growing a sub-collector contact layer, a bottom collector layer and a top collector layer on the substrate. Next, the substrate is removed from the molecular beam epitaxy machine and the top collector layer is etched by a photolithographic process to produce separate intrinsic and extrinsic collector regions. Then, the substrate is again loaded into the molecular beam epitaxy machine so that the base and emitter layers can be grown. And finally, the emitter layer is etched to form an emitter mesa only over the intrinsic semiconductor region.

Abstract: A self-aligned fully-walled monocrystalline silicon emitter-base structure for a bipolar transistor and methods for producing the structure are provided. The methods involve creating an oxide side wall surrounding a monocrystalline silicon emitter-base structure by first defining the emitter region in a base island region. Successive oxide layers are deposited on top of the emitter region and etched back to produce an oxide wall around the entire perimeter of the emitter region. In a preferred embodiment of the invention a metal silicide is also formed across the top of the base island region of the semiconductor outside of the emitter region. Since the extrinsic base region, outside of the oxide sidewalls, is entirely covered by a low resistance silicide film, the base contact area can be significantly reduced compared to prior art devices.The process results in a fully-walled emitter-base structure made of monocrystalline silicon which exhibits improved high-frequency performance.

Abstract: A field effect transistor includes a substrate of a compound semiconductor material, source and drain regions formed in the substrate, a channel region defined between the source and said drain regions, a gate electrode provided on the substrate so as to cover the channel region, and a pair of diffusion suppressing regions provided in the substrate respectively at both lateral ends of the channel region, each of the diffusion suppressing regions containing an electrically inert element that suppresses a diffusion of a dopant element therethrough.

Abstract: A liquid crystal display device includes a pair of substrates opposed to each other; a plurality of pixels for realizing display; and a liquid crystal layer interposed between the substrates and including a liquid crystal region corresponding to each of the pixels, the liquid crystal regions being surrounded by a polymer wall. At least one of the substrates is transparent and includes thereon an optical element for adjusting a transmittance of light therethrough. The optical element corresponds to each of the pixels. The optical element has a transmittance of no greater than 50% with respect to light of at least one wavelength in the range of 250 to 400 nm and has a maximum transmittance of at least 20% with respect to light of a wavelength of more than 400 nm.

Abstract: An integrated semiconductor device having a thyristor includes outer npn-transistors, outer pnp-transistors, and an inner npn-transistor. The outer pnp-transistors and the inner npn-transistor are interconnected so as to form a thyristor to allow the inner transistor to be biased into conduction. Furthermore, a current flow takes place via the outer npn-transistors and the inner npn-transistor. The integrated semiconductor device having a thyristor minimizes interference produced in neighboring components.

Abstract: A process for fabricating Ultra Large Scale Integrated (ULSI) circuits in Silicon On Insulator (SOI) technology in which the device structures, which can be bipolar, FET, or a combination, are formed in vertical silicon sidewalls having insulation under and in back thereof so as to create SKI device structures. The silicon sidewall device SOI structures, when fabricated, take the form of cells with each cell having a plurality of either bipolar devices, FET devices, or a combination of these devices, such as collectors, emitters, bases, sources, drains, and gates interconnected within the planes of the regions of the devices in the cells and can be interconnected within the planes of the regions of devices in adjacent cells. Further, the interconnections to adjacent cells can be made from the back of the silicon sidewalls.

Abstract: A bipolar transistor in accordance with the invention includes a polysilicon base contact (607A) which is self-aligned with a polysilicon emitter (303). The polysilicon emitter is formed from a first polysilicon layer overlying an intrinsic base region (502) in a substrate (201). An extrinsic base (504) in the substrate is in contact with the intrinsic base and is self-aligned with a spacer (406) adjacent to the emitter. The polysilicon base contact is formed from a second polysilicon layer (407) in contact with the extrinsic base and overlying the emitter. A second sidewall spacer (508) is formed on the second polysilicon layer on step caused by the emitter. A protective layer (509, 510) formed on portions of the second polysilicon layer protects the base contact when the second spacer and the underlying portion of the second polysilicon layer are removed.

Abstract: A TFT-LCD panel structure to prevent a TFT-LCD device provided therein from being damaged due to moisture penetration. The structure comprises upper and lower substrates and a display part having a thin film transistor array provided with a plurality of gate bus lines. A plurality of source bus lines are formed on the lower substrate and a pixel portion is formed on the upper substrate. A liquid crystal layer is formed between the substrates. Gate pad portions are formed at one side of the display part and include a plurality of gate pads connected to each corresponding gate bus line, for supplying a driving voltage to each of the gate bus lines through each corresponding gate pad. A first single passivation layer encloses each of the gate pad portions. Source pad portions are formed at upper and lower sides of the display part and include a plurality of source pads connected to each corresponding source bus line, for supplying a signal voltage to the source bus lines.

Abstract: A lateral bipolar transistor and method of making the transistor are disclosed. The device is made by etching a trench around a central region of a semiconductor body. An emitter is buried beneath the surface of this central area and contact to it is made via a self-alignment technique. The collector region of the transistor is contacted through the floor of the trench while the base region of the transistor is contacted in a region that surrounds the trench. The described method is compatible with the simultaneous manufacture of FET devices on the same chip.

Abstract: This invention describes a diving channel device structure and a method of forming the diving channel device structure using deep vertical trenches formed in a silicon substrate crossing shallow vertical trenches formed in the same silicon substrate. The deep vertical trenches are filled with a first heavily doped polysilicon to form the sources and drains of field effect transistors. The shallow vertical trenches are filled with a second highly doped polysilicon to form the gates of the transistors. The device structure provides reduced drain and source resistance which remains nearly constant when the device is scaled to smaller dimensions. The device structure also provides reduced leakage currents and a plane topography. The device structure forms a large effective channel width when the device is scaled to smaller dimensions.

Abstract: A multi-layer collector heterojunction transistor (10) provides for high power, high efficiency transistor amplifier operation, especially in the RF (radio frequency) range of operation. A larger band gap first collector layer (12), approximately 15% of the active collector region (11) thickness, is provided at the base-collector junction (13). A smaller band gap second collector layer (14) forms the remainder of the active collector region (11). The multi-layer collector structure provides higher reverse bias breakdown voltage and higher carrier mobility during relevant portions of the output signal swing. A lower saturation voltage limit, or "knee" voltage, is provided at the operating points where linear operating regions transition to saturation operating regions as depicted in the output voltage-current (I-V) characteristic curves. The magnitude of the output signal swing of an amplifier may be increased, providing higher power amplification with greater power efficiency.

Abstract: A semiconductor device having a structure capable of obtaining an increased alignment margin for a mask without any increase in the area of the semiconductor device by forming a contact plug on a drain while forming a contact pad on a source without forming contact plugs on both the source and the drain in a simultaneous manner, and a method for fabricating the semiconductor device. The contact pad has an upper portion partially overlapping with a portion of an insulating film surrounding a contact hole in which the contact pad is buried. Accordingly, it is possible to easily carry out the contact process.

Abstract: An object of the invention is to provide a capacitor having good anti-leak characteristics and good breakdown voltage characteristics. A transfer gate transistor having source/drain regions is formed on a surface of a silicon substrate. There is provided a lower electrode layer connected to the source/drain region through a plug layer which fills a contact hole formed at an interlayer insulating film. On the lower electrode layer, there is formed a capacitor insulating layer which includes a ferroelectric layer and exposes at least a sidewall surface of the lower electrode layer. The exposed sidewall surface of the lower electrode layer is covered with a sidewall insulating layer which is formed on a top surface of the interlayer insulating film and has a sidewall spacer configuration. The lower electrode layer is covered with an upper electrode layer with the sidewall insulating layer and capacitor insulating layer therebetween.

Abstract: A semiconductor device may include a double hetero junction bipolar transistor and a field-effect transistor. The base of the bipolar transistor and the gate of the field-effect transistor are connected to each other to serve as an input terminal and the collector of the bipolar transistor and the drain of the field-effect transistor are connected to each other to serve as an output terminal. The bipolar transistor and the field-effect transistor may be created on a common substrate. In this case, both the bipolar and field-effect transistors can have the same multilayer/film structures.

Abstract: A liquid crystal display comprises a pair of substrates, transparent electrodes respectively formed thereon and a liquid crystal material layer inserted between the electrodes, and is characterized in that a liquid crystalline polymer orientation layer is formed on at least one of the liquid crystal material layers, and the liquid crystalline polymer orientation layer functions as an optical phase retardation film. The phase retardation of the light transmitting liquid crystal layer is compensated by the liquid crystalline polymer orientation layer, which enhances contrast. The liquid crystalline polymer layer can also be used as an optical phase retardation film.

Abstract: An elevated source/drain structure is described in which the channel region is thinned by local oxidation and wet etch while the source/drain region remained thick. This structure achieves source/drain resistances as small as 300 ohm-.mu.m for NMOS, which makes possible high drive currents in deep submicron thin-film SOI/MOSFET.

Abstract: A method for manufacturing a semiconductor device such as a thin film transistor using a crystal silicon film is provided. The crystal silicon film is obtained by selectively forming films, particles or clusters containing nickel, iron, cobalt, ruthenium, rhodium, paradium, osmium, iridium, platinum, scandium, titanium, vanadium, chrome, manganese, copper, zinc, gold, silver or silicide thereof in a form of island, line, stripe, dot or film on or under an amorphous silicon film and using them as a starting point, by advancing its crystallization by annealing at a temperature lower than a normal crystallization temperature of an amorphous silicon. A transistor whose leak current is low and a transistor in which a mobility is high are obtained in the same time in structuring a dynamic circuit having a thin film transistor by selectively forming a cover film on a semiconductor layer which is to become an active layer of the transistor and by thermally crystallizing it thereafter.

Abstract: A hetero-bipolar transistor includes a collector layer of a first conductivity type, a base layer of a second conductivity type provided on the collector layer, a first emitter structure of the first conductivity type provided on the base layer, and a second emitter structure of the first conductivity type and provided on the base layer, wherein the first and second emitter structures are doped with respect to the base layer, with a sufficiently high impurity concentration level such that a Zener breakdown occurs at the p-n junction formed between the base layer and the first or second emitters upon application of a reverse bias voltage.