Abstract: There is provided a semiconductor device having a chip-size package structure comprising a semiconductor pellet including semiconductor elements, wires, a plurality of electrode pads, and final protection film, an insulation layer serving also as a sealing layer formed to cover the entire surface of the semiconductor pellet having a via hole portion above each of the electrode pads in association therewith, a plurality of wiring patterns formed with a via hole wiring portion electrically connected to the electrode pad at the bottom of each of the via hole portions of the insulation layer and formed with a land portion connected thereto and located in a position offset from the via hole portion, and an external electrode in the form of a ball provided on the land portion of each of the wiring patterns.

Abstract: A memory device of the present invention allows high integration, improved operational speed, larger capacitance, improved isolation and/or reduced leakage current. The memory device includes a plurality of transistors parallel to each other and formed above a substrate. A bit line is perpendicular to each of the plurality of transistors, and is coupled to the transistors. A predetermined portion of each transistor is a storage node for a capacitor, and a plate surrounds the predetermined portion through a dielectric film.

Abstract: A method for fabricating a solid-state image sensor includes the steps of forming a well of a first conductivity type in a substrate of a second conductivity type, forming a plurality of photoelectric conversion regions in the well, forming a plurality of charge coupled devices in the photoelectric conversion regions, forming a gate insulating layer over the substrate, forming a polysilicon layer over the gate insulating layer, forming a cap insulating layer over the polysilicon layer, forming a first optical shielding metal layer over the cap insulating layer, forming a first insulating layer over the first optical shielding metal layer, patterning the polysilicon layer, cap insulating layer, the first optical shielding metal layer, and the first insulating layer to form polygates, forming sidewall spacers on sides of the cap insulating layer and the polygate, forming a second optical shielding metal layer on sides of the first optical shielding metal layer and the sidewall spacers, and removing the first in

Abstract: A method of fabricating an integrated circuit transistor in a substrate is provided wherein a self-aligned gate electrode is formed after the high temperature steps associated with sidewall spacer formation and source/drain anneal. A first dielectric layer is formed on a substrate. First and second source/drain regions are formed in the substrate and spaced laterally to define a channel region underlying the first dielectric layer. A second dielectric layer is formed on the substrate except where the first dielectric layer is positioned. The first dielectric layer is removed and a third dielectric layer is formed that overlies the channel region. A gate electrode is formed on the third dielectric layer. The first dielectric layer functions as a disposable gate electrode to facilitate self-aligned source/drain implant and sidewall spacer formation.

Abstract: Leading and trailing metal features in a dense array of conductive lines bordering an open field are formed with side surfaces that gradually taper in the direction of the open field toward an underlying substrate. Each side surface bordering the open field is formed with a sufficient slope to reduce cracking of the subsequently deposited dielectric gap fill layer at high stress areas bordering the open field.

Abstract: The present invention relates to a semiconductor device whose through-holes are formed by self-alignment, and a method for fabricating the same. The through-holes formed on the gate electrodes can be formed simultaneously with SACs without complicating the fabrication process. The semiconductor device comprises a semiconductor substrate, a device isolation film defining devices regions on the semiconductor substrate, a pair of diffused layers formed in the device regions, gate electrodes formed through a first insulation film on the semiconductor substrate between the pair of diffused layers, and an etching stopper film covering side walls of the gate electrodes and parts of top surfaces of the gate electrodes which are extended inward by a prescribed distance from peripheral edges thereof. Whereby through-holes of an SAC structure can be formed in a later step, and the through-holes can be formed to expose the gate electrodes without removing the etching stopper film.

Abstract: An interconnect structure is centered around a substrate having multiple component contacts for receiving electronic components. Multiple conductive traces are provided over the substrate or in multiple layers of the substrate. Each conductive trace is connected to one of the component contacts. A programmable IC having a group of separate conductive leads is connected to the substrate. Two or more of the conductive leads are connected to corresponding ones of the conductive traces. The IC has programmable elements, such as electrically programmable elements, for selectively connecting the conductive leads, thereby enabling selected conductive traces to be interconnected so as to achieve a desired electrical function from the electronic components connected to the substrate. A test chip, an interconnect structure that contains the test chip, and a related test method are also provided.

Abstract: A semiconductor device in which stable and low resistance ohmic contact can be obtained in a base contact region without decreasing the emitter-base reverse breakdown voltage and the current amplification factor is disclosed. In this semiconductor device, p.sup.++ -type base contact layer 8 having an impurity concentration higher than that of p.sup.+ -type base layer 5 is formed in a region spaced apart by a predetermined distance from n.sup.+ -type emitter layer 7 on the main surface of p.sup.+ -type base layer 5. Thus, p.sup.++ -type base contact layer 8 having a high concentration does not contact n.sup.+ -type emitter layer 7, and also the current amplification factor and the emitter-base breakdown voltage are not decreased. Since p.sup.++ -type base contact layer 8 is formed so as to have a diffusion depth shallower than that of n.sup.+ -type emitter layer 7, the lateral spread of p.sup.++ -type base contact layer 8 can be reduced. Therefore, the side of p.sup.

Abstract: A semiconductor fabrication process in which nitrogen is incorporated into the transistor gate without significantly increasing the resistivity of the source/drain region. The incorporation of nitrogen into the gate structure substantially reduces the migration of impurity dopants from the silicon gate into the transistor channel region resulting in a more stable and reliable transistor. In one embodiment, a tail of the nitrogen impurity distribution incorporated into the gate structure extends into the channel region of the semiconductor substrate. In this embodiment, the nitrogen within the channel region prevents excessive lateral diffusion of source/drain impurities thereby permitting the fabrication of deep sub-micron transistors.

Abstract: A lead frame is prepared which has a plurality of leads whose inner lead portions are coupled to a support member and a notch formed across the bottom surface of each inner lead portion near at its front portion on the support member side. After an LSI chip is adhered to the support member, pads on the chip are connected via bonding wires to corresponding inner leads of the plurality of leads. The chip and inner lead portions are buried in an insulating layer made of resin or the like as protective coating. Each inner lead portion is cut with a cutting device such as laser beam at the notch position to separate the inner lead portion from the support member. Thereafter, the separated assembly unit is accommodated in a package made of resin or the like, and the outer leads are cut and shaped. For an assembly method of a semiconductor device including a wire bonding process, bonding defects to be caused by deformed leads can be reduced.

Abstract: A method of making a plug transistor is disclosed. The method includes providing a semiconductor substrate with an active region of a first conductivity type, providing a doped layer of a second conductivity type in the active region, forming a dielectric layer over the active region, forming an opening in the dielectric layer, implanting a dopant of the first conductivity type through the opening into a portion of the doped layer beneath the opening thereby counterdoping the portion of the doped layer and splitting the doped layer into source and drain regions, forming a gate insulator on the active region and in the opening, and forming a gate on the gate insulator and in the opening and adjacent to the dielectric layer. Preferably, a single photoresist layer provides an etch mask for the dielectric layer and an implant mask for the dopant.

Abstract: The present invention provides printed circuit boards for mounting to a semiconductor integrated circuit die. In one embodiment the printed circuit boards comprise a rigid dielectric substrate having a planar face, a plurality of circuit lines affixed to the face of the substrate, and a plurality of conductive bumps affixed to the face of the substrate. Each conductive bump has an upper bonding surface that is substantially planar and a lateral surface which is essentially perpendicular to the face of the substrate. The conductive bumps and the circuit lines are formed from a single metallic layer. The conductive bumps and circuit lines constitute a unitary, integral structure, i.e., each conductive bump and connecting circuit line lack a physical interface therebetween. The upper surfaces of the conductive bumps extend to essentially the same height above the surface of the substrate, i.e., the upper surfaces of the conductive bumps are substantially coplanar relative to each other.

Abstract: A method for forming a P-type region in a semiconducting crystalline substrate by ion implantation is disclosed, wherein the implant species is an ionic molecule that contains titanium and boron.

Abstract: In an integrated circuit type semiconductor device consisting of MISFETs, high rated voltage characteristic is obtained in a gate insulation film structure of a thin film. Further, a reduction in the manufacturing cost of semiconductor devices including high-rated voltage and low rated voltage MISFETs. An intermediate gate electrode is provided which overlies a channel formation region and a gate region with the same gate insulation film being sandwiched therebetween. The gate region is provided on the surface of a substrate. The channel formation region has an impedance indirectly controllable via the intermediate gate electrode upon application of a voltage to the gate region. The intermediate gate electrode is provided with a voltage reset(set) means connected thereto for eliminating the occurrence of charge-up.

Abstract: A field-effect transistor (10, FIG. 2) possesses improved electrostatic discharge characteristics. The transistor (10), formed in a p-type semiconductor substrate, comprises a gate (16) that forms a channel between two adjacent n-regions (12 and 14). At least one of the n-regions (12) has an n-well (22) below and centered about a contact pad (18). The n-well (22) has a second lower concentration of n-type impurities than either of the n-regions.

Abstract: An LDD structure is manufactured to have a desired aspect ratio of the height to the width of a gate electrode. The gate electrode is first deposited on a semiconductor substrate followed by ion implantation with the gate electrode as a mask to form a pair of impurity regions. The gate electrode is then anodic oxidized to form an oxide film enclosing the electrode. With the oxide film as a mask, highly doped regions are formed by ion implantation in order to define lightly doped regions between the highly doped regions and the channel region located therebetween.

Abstract: An inverter with an improved semiconductor device is provided having a pn junction composed of a first semiconductor layer made of a first conductivity type semiconductor and a second semiconductor layer made of a second conductivity type semiconductor having a wider band-gap than that of the first semiconductor layer.

Abstract: A semiconductor device comprises a reference voltage device for outputting a constant voltage, a voltage dividing device receptive of the constant voltage for dividing the constant voltage and outputting different currents, a digital signal processing device receptive of the different currents outputted by the voltage dividing device and outputting voltages, and a voltage amplifying device receptive of at least a ground voltage and one of the voltages outputted by the digital signal processing device and outputting a signal produced by amplifying the voltage of the digital signal processing device.

Abstract: A method for forming a dual gate oxide (DGO) structure begins by forming a first oxide layer (106) within active areas (110) and (112). A protection layer (108a) is then formed over the layer (106). A mask (114) is used to allow removal of the layers (106 and 108a) from the active area (110). A thermal oxidation process is then used to form a thin second oxide layer (118) within an active area (110). Conductive gate electrodes (120a and 120b) are then formed wherein the first oxide layer (106) and the protection layer (108c) are incorporated into the gate dielectric layer of an MOS transistor (122a). The transistor (122b) has a thinner gate oxide layer that excludes the protection layer (108c).

Abstract: A semiconductor device having the advantages of an SOI structure without the attendant disadvantages is obtained by implanting oxygen ions using the gate electrode as a mask, and heating to form thin, self-aligned buried oxide regions extending from a field oxide region under source/drain regions self-aligned with the side surfaces of the gate electrode. In other embodiments, the thin buried oxide layer extends from a point in close proximity to the field oxide region and/or partially under the gate electrode.