Abstract: A semiconductor device and fabrication thereof is disclosed in which devices are formed on two devices regions of opposite conductivity types by selectively masking and implanting the same type of dopant into active regions of both device regions. The process includes masking part of the active regions in each device region and implanting a dopant into exposed active regions in both devices regions. The number of masking, implantation and other steps required in the fabrication process are reduced by the selective masking of various active regions. Non-symmetrically doped source and drain regions may be formed on the transistors among a group which lie closest to the opposite device region.

Abstract: A semiconductor integrated circuit having a lateral bipolar transistor, is fabricated in a manner compatible with sub-micron CMOS processing. A base contact structure is formed over a bipolar active area, in essentially direct contact to a portion of the upper surface of the active region, essentially concurrent to the formation of a gate electrode on a gate dielectric layer in a CMOS active area. Sidewall spacers, adjacent the base contact region, are formed and a base region formed under the base contact structure using an oblique angle implantation. Emitter region and collector contact regions are formed concurrent with CMOS source and drain regions. An optional, oblique angle collector implant can be performed where desired.

Abstract: The present invention provides a method of fabricating fully dielectric isolated silicon (FDIS) by anodizing a buried doped silicon layer through trenches formed between active areas to form a porous silicon layer; oxidizing the porous silicon layer through the trenches to form a buried oxide layer; and by depositing a dielectric in the trenches. The process begins by forming a buried doped layer in a silicon substrate defining a silicon top layer over the conductive buried doped layer. The silicon top layer and the buried doped layer are patterned to form trenches that extend into but not through the buried doped layer. The trenches define isolated silicon regions. The buried doped layer is anodized to form a porous silicon layer. The porous silicon layer is converted into a buried oxide layer by oxidation. The oxidation step also forms a liner oxide layer on the tops and sidewalls of the isolated silicon regions.

Abstract: A high withstand voltage semiconductor device includes a semiconductor substrate of a first conductivity type, a metallic wiring formed on a surface of the semiconductor substrate and having a contact face with said semiconductor substrate, a highly doped impurity region formed within the semiconductor substrate below the contact face and of a second conductivity type, a lightly doped impurity region formed around the highly doped impurity region and of the second conductivity type, and a MOSFET with a second conductivity-type having a source or drain region formed on the surface of the semiconductor substrate and electrically connected to the metallic wiring through the impurity regions.

Abstract: A lateral silicon-controlled rectifier, which comprises a semiconductor layer of a first conductivity type, a floating semiconductor layer of a second conductivity type, a first doped region of the first conductivity type, a first doped region of the second conductivity type, and a second doped region of the first conductivity type, is disclosed. The floating semiconductor layer of a second conductivity type is in electrical contact with the semiconductor layer of a first conductivity type to establish a junction. The first doped region of the first conductivity type is formed in the semiconductor layer of a second conductivity type and coupled to a first node. Both the first doped region of the second conductivity type and the second doped region of the first conductivity type are formed in the semiconductor layer of a first conductivity type and coupled to a second node.

Abstract: A semiconductor device which achieves high-speed access and prevents the latch-up for any power inputting sequence by a plurality of power sources is disclosed. Where the chip voltage VDD is earlier inputted, an N well bias circuit 9 and a P well bias circuit 10 are activated, and an N-type well 12 and a P-type well 13 are biased respectively. After that, although the interface voltage VDDQ is inputted, the latch-up is not generated. On the other hand, where the interface voltage VDDQ is earlier inputted to a terminal 8, the N well bias circuit 9 and the P well bias circuit 10 are activated through a bypass circuit 15, and the N-type well 12 and the P-type well 13 are biased. Accordingly, although the chip voltage VDD is inputted after that, the latch-up is not generated.

Abstract: An electrostatic protection component and a method for forming the same. The method includes forming a gate consisting of a gate oxide layer and a conducting layer above a semiconductor substrate. Spacers are formed on the peripheral sidewalls of the gate. First heavily doped regions are formed in the semiconductor substrate. A metallic layer is formed covering the semiconductor substrate followed by a heating process. First metal silicide layers are formed above the gate while second metal silicide layers are formed above the first heavily doped regions. A photoresist layer is coated above the semiconductor substrate, exposing the first metal silicide layer and part of the second metal silicide layer adjacent to each side of the gate.

Abstract: A field effect transistor with a reduced delay variation is provided in a compound semiconductor layer with a channel, a source, and a drain region of a first conduction type. A gate electrode, a source electrode, and a drain electrode are formed respectively on the regions mentioned above. Particularly the gate electrode formed on the channel is provided with a projecting part extended in a direction crossing the direction of opposition of the source and drain region and caused to protrude from the channel region. In the compound semiconductor layer, a well region of a second conduction type opposite to the first conduction type is formed so as to enclose the channel region, the source region, the drain region, and the projecting part of the gate electrode more deeply than in the channel, source, and drain regions. The delay variation is markedly reduced by the fact that the gate electrode including the projecting part is enclosed with the well region of the second conduction type.

Abstract: A field effect transistor is formed across one or more trenches (26) or bars (120), thereby increasing the effective width of the channel region and the current-carrying capacity of the device.

Abstract: In the manufacture of CMOS devices, the n+ gate is partially counterdoped with boron to produce a modified p-type FET that has improved short channel effects, reduced gate induced drain leakage and gate oxide fields for improved reliability. A doped polysilicon layer is formed over a silicon or silicon oxide substrate, and is counterdoped with boron to a level of about 1.times.10.sup.13 /cm.sup.2 to 5.times.10.sup.16 /cm.sup.2 to adjust the work function but without changing the essentially n-type character of the gate electrode. This single counterdoping step achieves improved results for sub-micron devices at low cost. For CMOS device manufacturing, the alternating n-type and p-type devices are made in similar manner but reversing the n-type and p-type dopants.

Abstract: A transient suppressor comprises a self-triggered silicon control rectifier (SCR) that forms a drive circuit for an NPN power transistor. The SCR and the NPN power transistor are combined, along with other elements, into an integrated circuit (IC) by a junction isolated BiCMOS process. The SCR self-triggers upon being subjected to an inductive flyback condition created by an inductive load and renders the NPN transistor conductive, thereby allowing the NPN power transistor, having a relatively large semiconductor region, to effectively snub the current created by the negative feedback condition. The transient suppressor may be used in either a high-side or low-side driver arrangement and the SCR/NPN power transistor combination may further be combined with load driving and other circuitry on a single integrated circuit.

Abstract: The present invention discloses a high voltage semiconductor device with high breakdown voltage without increment in area occupied an increase in the size of junction region. Each junction region includes: (i) a first impurity region of a first conductivity type of a low impurity concentration formed at a predetermined position in the semiconductor substrate, (ii) a second impurity region of a second conductivity type of a medium impurity concentration formed in the first impurity region, a part of the second impurity region being exposed to the surface of the substrate, and (iii) a third impurity region of a first conductivity type of a high impurity concentration, the third impurity region being in contact with the second impurity region, wherein a reverse bias is applied to the third impurity region.

Abstract: A merged single polysilicon bipolar NPN transistor, rather than using separate isolation islands for emitter-base and collector contacts, utilizes a single isolation island. This significantly reduces device area because elimination of the second isolation island used in conventional designs reduces the N+ sink to NPN spacing. Buried layer and isolation layer processing proceed in the conventional manner. At sink mask, however, the mask is sized to uncover one end of the main device active region and a sink implant is performed. At base mask, the sink implant remains covered, rather than being exposed as in the conventional flow. At silicide exclusion, the oxide spacer layer is patterned to exclude silicide from the area above the sink implant region.

Abstract: The invention concerns a semiconductor component which can be controlled on the anode side and whose semiconductor body comprises a plurality of adjacent, parallel-connected unit cells having a thyristor structure. A lightly doped n-base region (3) is adjoined on both sides by highly doped p-regions constituting p-base region (2) and p-emitter region (4). The p-base region (2) is followed by a highly doped n-emitter (1) which contacts a cathode electrode (7). Integrated in the p-emitter region (4) is a first n-channel MOSFET (M1) which is connected in series with the thyristor structure by means of a floating electrode (FE). The drain electrode (5b) of the first MOSFET (M1) is provided with an outer anode (8) which has no contact with the p-emitter region (4). A second n-channel MOSFET (M2) is integrated between the n-base region (3) and the drain region (5b) of the first MOSFET (M1).

Abstract: A sub-gate electrode is arranged to face, through a gate insulating film, a surface of a first p-type base layer which is interposed between a first n-type source layer and an n-type drift layer, and a surface of a second p-type base layer which is interposed between a second n-type source layer and the n-type drift layer and faces the first p-type base layer. A main gate electrode is arranged to face, through a gate insulating film, a surface of the second p-type base layer which is interposed between the second n-type source layer and the n-type drift layer and does not face the first p-type base layer. Three n-type MOSFETs are constructed such that one n-type channel is to be formed in the first p-type base layer and two n-type channels are to be formed in the second p-type base layer. The three channels are to be formed, so that the channel width is effectively enlarged and the current density is increased. The second p-type base layer has a length of 10 .mu.m or less in the drifting direction.

Abstract: The present invention relates to Silicon Germanium-based Vertical MISFET devices allowing smaller device size and exhibiting significant advantages over prior devices related to the reduction of drain induced barrier lowering and parasitic capacitance and permitting a higher integration density.

Abstract: In a semiconductor device having a PN junction element separating region, in order to reduce a width of the PN junction element separating region without sacrifice of a punch-through breakdown voltage of the PN junction element separating region, the PN junction element separating region is composed of an upper impurity layer of a first conductivity type having low impurity density and a lower impurity layer of the first conductivity type having a high impurity density and a width of the upper impurity layer is smaller than a width of the lower impurity layer.

Abstract: A semiconductor device includes a semiconductor element, such as a field effect transistor, and an adjacent connection region including a via hole. A simple structure prevents leakage current from flowing from a p-type buffer layer to a source electrode of the field effect transistor through a backside electrode and a via hole upper electrode, avoiding degradation in the gate-source dielectric resistance. A groove having a depth extending from a surface of an n-type semiconductor layer through a n-type semiconductor layer and a p-type buffer layer isolates a field effect transistor from a via hole that extends from the surface of an n-type semiconductor layer to a second surface of a compound semiconductor substrate. The groove prevents leakage current from flowing in a backside electrode in the via hole.

Abstract: A power semiconductor structure (200), in particular in VIPower technology, made from a chip of N-type semiconductor material (110), comprising a bipolar or field-effect vertical power transistor (125, 120, 110) having a collector or drain region in such N-type material (110); the semiconductor structure comprises a PNP bipolar lateral power transistor (210, 110, 220) having a base region in such N-type material (110) substantially in common with the collector or drain region of the vertical power transistor.

Abstract: A WSi film is deposited on a semi-insulative GaAs substrate. Thereafter, a first Al mask and a second SiO.sub.2 mask are formed such that these two masks overlap on the WSi film. A SF.sub.6 /CF.sub.4 mixture, which contains a gas of SF.sub.6 in an amount of more than 20%, is used to dry-etch the WSi film. The WSi film is T-shaped, in other words the WSi film becomes gradually downwardly narrower in lateral length. The second mask is stripped. A .GAMMA.-shaped gate electrode is formed by means of an anisotropic etching process. Subsequently, an isotropic etching process is carried out to reduce the gate length of the electrode down to 0.5 .mu.m or less. Silicon ions are implanted to form individual n' layers. A through film is deposited. Silicon ions are implanted to form individual n.sup.+ layers.