Abstract: A method of forming an electronic device on a semiconductor substrate includes forming first and second field effect transistors on a substrate. In particular, the first field effect transistor includes a first gate dielectric layer having a first nitrogen concentration, and the second field effect transistor includes a second gate dielectric layer having a second nitrogen concentration lower than the first nitrogen concentration. More particularly, the first field effect transistor can be a PMOS transistor, and the second field effect transistor can be an NMOS transistor. Related structures are also discussed.

Abstract: In a semiconductor apparatus comprises a signal input portion having an amplifying circuit including one, two or more insulating gate type transistors (MIS Tr), one MIS Tr or at least one (M1) of the two or more MIS Trs of the signal input portion is an MIS Tr of one conductivity channel type. The MIS Tr (M1) of the one conductivity channel type is formed in a semiconductor region which is electrically isolated from the other MIS Tr (M3) of one conductivity channel type provided for a circuit portion other than the signal input portion, so that an input threshold level of the signal amplifying circuit is made coincide with a DC level of the input signal, thereby preventing an erroneous operation.

Abstract: In a MOSFET having a polysilicon gate electrode, the polysilicon layer of the gate electrode is nonuniformly doped with an impurity for the same type of conductivity as the source and drain regions such that the effective impurity concentration gradually and continuously decreases from a top section toward a bottom section adjacent to the gate oxide film and becomes minimum in the bottom section. When a high voltage is applied between the drain and the gate, a depletion layer is created in the bottom section of the polysilicon layer, whereby the electric field on the gate oxide film is reduced. Accordingly, the thickness of the gate oxide film can be reduced for high-speed operation. Besides, this MOSFET is useful in a high-voltage interface for a MOS circuit operated at a low supply voltage. The doping of the polysilicon layer is accomplished by ion implantation. It is suitable to employ a lightly doped drain (LDD) structure in this MOSFET.

Abstract: A MESFET has a metallic laminate including WSi.sub.x, Ti, Pt and Au films and implementing gate, source and drain electrodes of the MESFET and interconnects therefor. The substrate of the MESFET is formed of a substrate body, a first semiconductor layer made of n.sup.+ -GaAs doped with Si at a concentration of 2.times.10.sup.18 atoms/cm.sup.3 and a second semiconductor layer made of n.sup.+ -InGaAs doped with Si at a concentration of 1.times.10.sup.19 atoms/cm.sup.3. The source and drain electrodes contact the second semiconductor layer in an ohmic contact while the gate electrode contacts the first semiconductor layer in a Schottky contact through a hole formed in the second semiconductor layer. A reduced number of steps in manufacture of the MESFET can be obtained, thereby reducing fabrication costs of the MESFET.

Abstract: A MOS technology power device comprises a semiconductor material layer of a first conductivity type, a conductive insulated gate layer covering the semiconductor material layer, and a plurality of elementary functional units. The conductive insulated gate layer includes a first insulating material layer placed above the semiconductor material layer, a conductive material layer placed above the first insulating material layer, and a second insulating material layer placed above the conductive material layer. Each elementary functional unit includes an elongated body region of a second conductivity type formed in the semiconductor material layer. Each elementary functional unit further includes an elongated window in the insulated gate layer extending above the elongated body region. Each elongated body region includes a source region doped with dopants of the first conductivity type, intercalated with a portion of the elongated body region wherein no dopant of the first conductivity type are provided.

Abstract: A silicon oxide layer serving as an insulation layer is formed on a p-type semiconductor substrate. An n.sup.+ -type source and drain regions are formed on the p-type substrate 110 with a spacing therebetween. A channel region is interposed between the source and drain regions. A silicon oxide layer serving as an insulation layer is formed on the channel region. A gate terminal is formed on the silicon oxide layer. High-concentration p-type regions are formed in the p-type semiconductor substrate under the source and drain regions, respectively.

Abstract: An asymmetrical N-channel IGFET and a symmetrical P-channel IGFET are disclosed. The N-channel IGFET includes heavily doped and ultra-heavily doped source regions, and lightly doped and heavily doped drain regions. The P-channel IGFET includes lightly doped and heavily doped source and drain regions.

Abstract: A semiconductor device includes a p channel MOS transistor with a p.sup.- diffusion region, a p.sup.+ diffusion region and a gate electrode formed on the main surface of an n.sup.- layer on a buried oxide film. The p.sup.- diffusion region includes a plurality of branch-like regions to be connected to a p.sup.+ diffusion region. A source electrode is formed at the p.sup.+ diffusion region. An n.sup.+ diffusion region is formed within the p.sup.+ diffusion region. A drain electrode is connected to the p.sup.+ diffusion region and the n.sup.+ diffusion region. According to this structure, the depletion layer between the source electrode and the drain electrode is expanded. A semiconductor device is achieved that is improved in the breakdown voltage at the time of an off operation, or that is improved in on driving current at the time of an on operation with improved breakdown voltage at the time of an off operation.

Abstract: A CMOS integrated circuit having a PMOS and NMOS device with different gate dielectric layers. According to the present invention, an NMOS transistor is formed on a p-type conductivity region of a semiconductor substrate. The NMOS transistor has first gate dielectric layer formed on the p-type conductivity region. A PMOS transistor is formed on a n-type conductivity region of the semiconductor substrate. The PMOS transistor has a second gate dielectric layer wherein the second gate dielectric layer has a different composition than the first gate dielectric layer.

Abstract: A method of fabricating a thin film transistor includes the steps of forming an active layer on an insulating substrate; forming an insulating layer and a first metal layer on the active layer; forming a photoresist pattern for forming a gate electrode on the metal layer; etching the metal layer and the insulating layer by using the photoresist pattern as a mask, and respectively forming a gate electrode and a gate insulating layer to expose a part of the active layer; forming an amorphous silicon layer on the resultant whole surface of the substrate; forming a second metal layer on the amorphous silicon layer; patterning the second metal layer and the amorphous silicon layer by a photolithographic process to form an offset layer and a source/drain electrode; and carrying out a lift-off process to remove the photoresist pattern, and exposing the surface on the gate electrode.

Abstract: A method for forming an interconnect structure on a semiconductor wafer (114) begins by placing the wafer (114) in a process chamber (100). The process chamber (100) contains a titanium (Ti) target (102) having a thin titanium nitride (TiN) layer (104) formed thereon. An argon-based plasma (106) is used to sputter the layer (104) off of the target (102) and onto a top surface of the water (114) to form an Argon Uniquely Sputtered Titanium Nitride (AUSTiN) layer (116) which has a nitrogen concentration gradient therethrough. After forming the layer (116), an argon-nitrogen plasma (107) is initiated to reform the titanium nitride (TiN) layer (104) on the target and complete the interconnect structure by forming a top stoichiometric or near stoichiometric titanium nitride layer (118) over the layer (116).

Abstract: A method of forming an isolation region in an integrated circuit and an integrated circuit formed thereby. A method preferably includes forming at least one trench in a semiconductor substrate, forming an insulation layer of material in the at least one trench and on peripheral regions of the at least one trench of the semiconductor substrate, forming a sacrificial layer of material on the insulation layer having a different polishing rate than the insulation layer, and polishing the layer having the different polishing rate and portions of the insulation layer so that the sacrificial layer having the different polishing rate and portions of the insulation layer are removed, so that other portions of the insulation layer remain in the at least one trench of the substrate, and so that the upper surface of the at least one trench and the peripheral regions thereof in combination provide a substantially planar surface.

Abstract: There is provided a method of fabricating a semiconductor device including, a first conductivity type MOSFET, a second conductivity type MOSFET, and a power MOSFET having a high breakdown voltage, and having a drain offset region formed in the substrate between the drain region and a channel region located below the gate electrode, and containing first conductivity type impurities therein at such a concentration that carriers are depleted in an operation of the semiconductor device, the method including the steps, in sequence, of (a) forming gate electrodes on the substrate in first, second and third regions where the first conductivity type MOSFET, the second conductivity type MOSFET, and the power MOSFET are to be fabricated, respectively, (b) introducing first conductivity type impurities into the substrate at such a concentration that carriers are depleted in an operation of the semiconductor device, (c) introducing first conductivity type impurities into the substrate with both the second region and a re

Abstract: A system and method for providing at least one memory cell on a semiconductor is disclosed. The method and system include providing a tunneling barrier on the semiconductor, providing at least one floating gate having a corner, and oxidizing the tunneling barrier, a portion of the semiconductor, and the at least one floating gate. A portion of the at least one floating gate including the corner is disposed above the tunneling barrier. The portion of the semiconductor oxidizes at a first rate and at least the corner of the at least one floating gate oxidizes at a second rate. The second rate is sufficiently higher than the first rate to provide a desired thickness of the tunneling barrier a distance from the corner of the at least one floating gate for a particular rounding of the corner of the at least one floating gate.

Abstract: The present invention discloses a method for forming a DRAM capacitor that has improved charge storage capacity by utilizing a deposition process wherein alternating layers of doped and undoped dielectric materials are first deposited, a deep UV type photoresist layer is then deposited on top of the oxide layers such that during a high density plasma etching process for the cell opening, acidic reaction product is generated by the photoresist layer when exposed to UV emission in an etch chamber such that the sidewall of the cell opening is etched laterally in an uneven manner, i.e., the doped dielectric layer being etched more severely than the undoped dielectric layer thus forming additional surface area and an improved charge storage capacity for the capacitor formed.

Abstract: Process for making an integrated-circuit (IC) chip with junction-isolated complementary bipolar transistors. In this process an N-well is formed in a P-type substrate. P-type dopant is implanted in the N-well to become a sub-collector for a pnp transistor. N-type dopant is implanted in the substrate in a location laterally displaced from the N-well to become a sub-collector for an npn transistor. N-type material is implanted in the N-well to begin the formation of an isolation wall for the pnp transistor. A P-type epitaxial (epi) layer then is grown over the P-type substrate. N-type material is implanted in the epi layer to complete the isolation wall for the pnp transistor, and to complete the collector for the npn transistor. P-type and N-type material also is implanted in the P-type epi layer to form the bases and emitters for the npn and pnp transistors.

Abstract: A monolthically integrated VCSEL and photodetector, and a method of manufacturing same, are disclosed for applications where the VCSEL and photodetector require separate operation such as duplex serial data communications applications. A first embodiment integrates a VCSEL with an MSM photodetector on a semi-insulating substrate. A second embodiment builds the layers of a p-i-n photodiode on top of layers forming a VCSEL using a standard VCSEL process. The p-i-n layers are etched away in areas where VCSELs are to be formed and left where the photodetectors are to be formed. The VCSELs underlying the photodetectors are inoperable, and serve to recirculate photons back into the photodetector not initially absorbed. The transmit and receive pairs are packaged in a single package for interface to multifiber ferrules. The distance between the devices is precisely defined photolithographically, thereby making alignment easier.

Abstract: An adhesion pad for adhering a semiconductor chip or a ball grid array module to a supporting substrate includes a stepped or tapered structure. The structure is composed of at least one solder wettable metal or alloy layer having solder deposited thereon. The stepped or tapered structure prevents a fatigue crack from propagating in the X-Y plane above the adhesion pad.

Abstract: A bipolar fabrication process, illustratively suited for integration into a conventional CMOS process to thereby form a BiCMOS integrated circuits is disclosed. The collector and base are formed through multiple implants and a single masking step to thereby provide a continuous low resistance collector region.

Abstract: A semiconductor device comprising a first electrically conductive layer formed on a semiconductor element or on one main surface of a semiconductor substrate, an insulating layer formed on said first electrically conductive layer through which a connection hole of which diameter is the smallest in a portion other than the bottom is formed, and a second electrically conductive layer formed on said insulating layer.