Patents Examined by Wai-Sing Louie
  • Patent number: 8575726
    Abstract: A semiconductor device includes: a semiconductor chip including: a first main face having an edge portion, a second main face locating the opposite side to the first main face, a crystalline defect region present within a region including at least the edge portion being adjacent to the first main face, the crystalline defect region being configured to have lower stress than the stress in the other semiconductor region for the same strain; and a metallic substrate to be bonded via a bonding member to the first main face of the semiconductor chip.
    Type: Grant
    Filed: March 6, 2008
    Date of Patent: November 5, 2013
    Assignee: Nissan Motor Co., Ltd.
    Inventor: Yoshinori Murakami
  • Patent number: 8436385
    Abstract: A light emitting device package is provided. The light emitting device package comprises a package body comprising a first cavity, and a second cavity connected to the first cavity; a first lead electrode, at least a portion of which is disposed within the second cavity; a second lead electrode, at least a portion of which is disposed within the first cavity; a light emitting device disposed within the second cavity; a first wire disposed within the second cavity, the first wire electrically connecting the light emitting device to the first lead electrode; and a second wire electrically connecting the light emitting device to the second lead electrode.
    Type: Grant
    Filed: May 24, 2011
    Date of Patent: May 7, 2013
    Assignee: LG Innotek Co., Ltd.
    Inventors: Wan Ho Kim, Jun Seok Park
  • Patent number: 8436441
    Abstract: A photoelectric conversion device comprising a photoelectric conversion part including a first electrode layer, a second electrode layer and a photoelectric conversion layer provided between the first electrode layer and the second electrode layer, wherein light is made incident from an upper part of the second electrode layer into the photoelectric conversion layer; the photoelectric conversion layer generates a charge containing an electron and a hole corresponding to the incident light from the upper part of the second electrode layer; and the first electrode layer works as an electrode for extracting the hole.
    Type: Grant
    Filed: April 22, 2011
    Date of Patent: May 7, 2013
    Assignee: FUJIFILM Corporation
    Inventors: Tetsuro Mitsui, Daisuke Yokoyama
  • Patent number: 8431982
    Abstract: A semiconductor device includes capacitors connected in parallel. Electrode active portions and a discharge active portion are defined on a semiconductor substrate, and capping electrodes are disposed respectively on the electrode active portions. A capacitor-dielectric layer is disposed between each of the capping electrodes and each of the electrode active portions that overlap each other. A counter doped region is disposed in the discharge active portion. A lower interlayer dielectric covers the entire surface of the semiconductor substrate. Electrode contact plugs respectively contact the capping electrodes through the lower interlayer dielectric, and a discharge contact plug contacts the counter doped region through the lower interlayer dielectric. A lower interconnection is disposed on the lower interlayer dielectric and contacts the electrode contact plugs and the discharge contact plug.
    Type: Grant
    Filed: January 19, 2011
    Date of Patent: April 30, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Myoungsoo Kim, Yoonkyung Choi, Eun Young Lee, Sungil Jo
  • Patent number: 8426864
    Abstract: The infrared sensor (1) includes a base (10), and an infrared detection element (3) formed over a surface of the base (10). The infrared detection element (3) comprises an infrared absorption member (33) in the form of a thin film configured to absorb infrared, and a temperature detection member (30) configured to measure a temperature difference between the infrared absorption member (33) and the base (10). The temperature detection member (30) includes a p-type polysilicon layer (35) formed over the infrared absorption member (33) and the base (10), an n-type polysilicon layer (34) formed over the infrared absorption member (33) and the base (10) without contact with the p-type polysilicon layer (33), and a connection layer (36) configured to electrically connect the p-type polysilicon layer (35) to the n-type polysilicon layer (34). Each of the p-type polysilicon layer (35) and the n-type polysilicon layer (34) has an impurity concentration in a range of 1018 to 1020 cm?3.
    Type: Grant
    Filed: September 24, 2009
    Date of Patent: April 23, 2013
    Assignee: Panasonic Corporation
    Inventors: Koji Tsuji, Yosuke Hagihara, Naoki Ushiyama
  • Patent number: 8426852
    Abstract: Transistors and electronic apparatuses including the same are provided, the transistors include a channel layer on a substrate. The channel layer includes a zinc (Zn)-containing oxide. The transistors include a source and a drain, respectively, contacting opposing ends of the channel layer, a gate corresponding to the channel layer, and a gate insulating layer insulating the channel layer from the gate. The channel layer has a first surface adjacent to the substrate, a second surface facing the first surface, and a channel layer-protection portion on the second surface. The channel layer-protection portion includes a fluoride material.
    Type: Grant
    Filed: September 1, 2010
    Date of Patent: April 23, 2013
    Assignees: Samsung Electronics Co., Ltd., SNU R&DB Foundation
    Inventors: Jae-cheol Lee, Chang-seung Lee, Jae-gwan Chung, Eun-ha Lee, Anass Benayad, Sang-wook Kim, Se-jung Oh
  • Patent number: 8415813
    Abstract: A semiconductor wafer includes multiple dies and a die identification region adjacent to or on each die. The die identification region can include a wafer indicator and a pattern of die locations representing die locations on the wafer. A die identification marker is provided in each pattern of die locations in the die identification region specifying a location of a respective die on the wafer.
    Type: Grant
    Filed: June 15, 2011
    Date of Patent: April 9, 2013
    Assignee: Truesense Imaging, Inc.
    Inventors: Shen Wang, Robert P. Fabinski, James E. Doran, Laurel J. Pace, Eric J. Meisenzahl
  • Patent number: 8410393
    Abstract: A recirculation system of a substrate support on which a semiconductor substrate is subjected to a multistep process in a vacuum chamber, the system comprising a substrate support having at least one liquid flow passage in a base plate thereof, an inlet and an outlet in fluid communication with the flow passage, a supply line in fluid communication with the inlet, and a return line in fluid communication with the outlet; a first recirculator providing liquid at temperature T1 in fluid communication with the supply line and the return line; a second recirculator providing liquid at temperature T2 in fluid communication with the supply line and the return line, temperature T2 being at least 10° C. above temperature T1; a pre-cooling unit providing liquid at temperature Tpc connected to the inlet and the outlet, temperature Tpc being at least 10° C. below T1; a pre-heating unit providing liquid at temperature Tph connected to the inlet and the outlet, temperature Tph being at least 10° C.
    Type: Grant
    Filed: May 24, 2010
    Date of Patent: April 2, 2013
    Assignee: Lam Research Corporation
    Inventors: Anthony Ricci, Saurabh Ullal, Michael Kang, Matthew Busche
  • Patent number: 8394652
    Abstract: A light emitting element having a recess-protrusion structure on a substrate is provided. A semiconductor light emitting element 100 has a light emitting structure of a semiconductor 20 on a first main surface of a substrate 10. The first main surface of the substrate 10 has substrate protrusion portion 11, the bottom surface 14 of each protrusion is wider than the top surface 13 thereof in a cross-section, or the top surface 13 is included in the bottom surface 14 in a top view of the substrate. The bottom surface 14 has an approximately polygonal shape, and the top surface 13 has an approximately circular or polygonal shape with more sides than that of the bottom surface 14.
    Type: Grant
    Filed: June 15, 2010
    Date of Patent: March 12, 2013
    Assignee: Nichia Corporation
    Inventors: Shunsuke Minato, Junya Narita, Yohei Wakai, Yukio Narukawa, Motokazu Yamada
  • Patent number: 8395078
    Abstract: A system and method for managing power delivered to a processing chamber is described. In one embodiment current is drawn away from the plasma processing chamber while initiating an application of power to the plasma processing chamber during an initial period of time, the amount of current being drawn away decreasing during the initial period of time so as to increase the amount of power applied to the plasma processing chamber during the initial period of time.
    Type: Grant
    Filed: December 4, 2009
    Date of Patent: March 12, 2013
    Assignee: Advanced Energy Industries, Inc
    Inventor: Milan Ilic
  • Patent number: 8389405
    Abstract: A method for forming a fine pattern having a variable width by simultaneously using an optimal focused electron beam and a defocused electron beam in a light exposure process Includes, after forming a first film on a substrate, forming a first film pattern including a first level area and a second level area having different distances from the substrate by changing a profile of an upper surface of the first film. A photoresist film having a first area covering the first level area and a second area covering the second level area is formed. To simultaneously light-expose the first area and the second area with the same width, a light exposure condition, in which an optimal focused electron beam is eradiated on the first area and a defocused electron beam is eradiated on the second area, is applied.
    Type: Grant
    Filed: August 30, 2010
    Date of Patent: March 5, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Yong-ju Jung
  • Patent number: 8390115
    Abstract: Provided is a wiring board wherein a circuit is not short-circuited when a IC chip is mounted on the wiring board. A wiring board (2) is provided with a substrate (4); wiring layers (5-8), which are formed on a surface of the substrate (4) and have prescribed wiring patterns; connecting terminals (9-12), which are formed on a part of the wiring layers (5-8) and electrically connected with bumps (18-21) of an integrated circuit chip (IC chip) (3); a mounting region (14), which is arranged on the surface of the substrate (4) and has the integrated circuit chip (3) mounted therein; and an insulating layer (13), which is formed on the surface of the substrate (4) so as to surround the circumference of the mounting region (14) for protecting wiring layers (5-8). A part of the insulating layer (3) is arranged inside the mounting region (14), and the thickness of the insulating layer (13) is more than that of the bumps (18-21) of the integrated circuit chip (3).
    Type: Grant
    Filed: March 6, 2009
    Date of Patent: March 5, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Hiroki Nakahama
  • Patent number: 8390027
    Abstract: A gallium nitride semiconductor device is disclosed that can be made by an easy manufacturing method. The device includes a silicon substrate, buffer layers formed on the top surface of the silicon substrate, and gallium nitride grown layers formed thereon. The silicon substrate has trenches 12 formed from the bottom surface, each trench having a depth reaching the gallium nitride grown layer through the silicon substrate and the buffer layers. The inside surface of each of the trenches and the bottom surface of the silicon substrate is covered with a drain electrode as a metal film. The vertical gallium nitride semiconductor device with this structure allows an electric current to flow in the direction of the thickness of the silicon substrate regardless of the resistance values of the gallium nitride grown layers and the buffer layers.
    Type: Grant
    Filed: October 1, 2008
    Date of Patent: March 5, 2013
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Noriyuki Iwamuro
  • Patent number: 8384108
    Abstract: A light emitting device package is provided. The light emitting device package comprises a package body comprising a first cavity, and a second cavity connected to the first cavity; a first lead electrode, at least a portion of which is disposed within the second cavity; a second lead electrode, at least a portion of which is disposed within the first cavity; a light emitting device disposed within the second cavity; a first wire disposed within the second cavity, the first wire electrically connecting the light emitting device to the first lead electrode; and a second wire electrically connecting the light emitting device to the second lead electrode.
    Type: Grant
    Filed: May 24, 2011
    Date of Patent: February 26, 2013
    Assignee: LG Innotek Co., Ltd.
    Inventors: Wan Ho Kim, Jun Seok Park
  • Patent number: 8377747
    Abstract: A method of making an IC device includes providing a stack of leadframe sheets each including a plurality of leadframes and an interleaf member interposed between adjacent ones of the leadframe sheets. The interleaf members include indicia that identifies the leadframes sheets. The stack of leadframe sheets is loaded onto an assembly machine. A first interleaf member is removed from the first leadframe sheet. The first leadframe sheet is transferred onto a mounting surface of the assembly machine. Semiconductor die are attached to leadframes on the first leadframe sheet. The method can include reading the indicia from the first interleaf member to determine a part number and lead finish for the first leadframe sheet, verifying the part number for the first leadframe sheet by comparing to a build list, and transferring the first leadframe sheet onto a mounting surface of the assembly machine only if the part number is verified.
    Type: Grant
    Filed: August 27, 2010
    Date of Patent: February 19, 2013
    Assignee: Texas Instruments Incorporated
    Inventor: John Paul Tellkamp
  • Patent number: 8378392
    Abstract: A trench Metal Oxide Semiconductor Field Effect Transistor with improved body region structures is disclosed. By forming the inventive body region structures with concave-arc shape with respect to epitaxial layer, a wider interfaced area between the body region and the epitaxial layer is achieved, thus increasing capacitance between drain and source Cds. Moreover, the invention further comprises a Cds enhancement doped region interfaced with said body region having higher doping concentration than the epitaxial layer to further enhancing Cds without significantly impact breakdown voltage.
    Type: Grant
    Filed: April 7, 2010
    Date of Patent: February 19, 2013
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Patent number: 8377813
    Abstract: A method for forming a buried split word line structure is provided. The method comprises the following steps. At first, a substrate having a trench therein is provided. Two liners are formed to a first thickness on sidewalls of the trench. Then, the trench is filled with a first insulating layer to a first height. The two liners are removed. Finally, a conductive material is deposited to a second height between and adjacent to the first insulating layer and the trench. Here, the first height is greater than the second height.
    Type: Grant
    Filed: August 27, 2010
    Date of Patent: February 19, 2013
    Assignee: Rexchip Electronics Corporation
    Inventor: Chih-Hao Lin
  • Patent number: 8378333
    Abstract: An apparatus, system, and method are provided for a lateral two-terminal nanotube device configured to capture and generate energy, to store electrical energy, and to integrate these functions with power management circuitry. The lateral nanotube device can include a substrate, an anodic oxide material disposed on the substrate, and a column disposed in the anodic oxide material extending from one distal end of the anodic oxide material to another end of the anodic oxide material. The lateral nanotube device further can include a first material disposed within the column, and a second material disposed within the column. The first material fills a distal end of the column and gradiently decreases towards another distal end of the column along inner walls of the column. The second material fills the another distal end of the column and gradiently decreases towards the distal end of the column within the first material.
    Type: Grant
    Filed: September 26, 2008
    Date of Patent: February 19, 2013
    Assignee: University of Maryland
    Inventors: Parag Banerjee, Sang Bok Lee, Israel Perez, Erin Robertson, Gary W. Rubloff
  • Patent number: 8378461
    Abstract: A light-emitting device comprises a substrate that has a contact plug extending therethrough between first and second opposing surfaces. An active region is on the first surface, a first electrical contact is on the active region, and a second electrical contact is adjacent to the second surface of the substrate. The contact plug couples the second electrical contact to the active region. Such a configuration may allow electrical contacts to be on opposing sides of a chip, which may increase the number of devices that may be formed on a wafer.
    Type: Grant
    Filed: May 11, 2009
    Date of Patent: February 19, 2013
    Assignee: Cree, Inc.
    Inventor: Gerald H. Negley
  • Patent number: 8373180
    Abstract: A side-view type light emitting diode package for emitting light, emitted from a light emitting diode chip, toward a side surface is disclosed. The side-view type light emitting diode package comprises a package body having an opening portion for exposing the light emitting diode chip in a light emitting direction; and a light-transmittable resin covering the light emitting diode chip, wherein at least a portion of an inner wall of the opening portion is formed with a step projection for partitioning the opening portion into upper and lower sections, and the lower section of the opening portion below the step projection is filled with the light-transmittable resin. Accordingly, the light-transmittable resin with the convex lens shape may be easily formed, so that the light emission efficiency thereof can be improved.
    Type: Grant
    Filed: September 21, 2007
    Date of Patent: February 12, 2013
    Assignee: Seoul Semiconductor Co., Ltd.
    Inventors: Hwa Ja Kim, Nam Young Kim, Myung Hee Lee, Kyoung Bo Han, Tae Kwang Kim, Ji Seop So