Patents Examined by Wai-Sing Louie
  • Patent number: 8338856
    Abstract: A backside illuminated (“BSI”) complementary metal-oxide semiconductor (“CMOS”) image sensor includes a photosensitive region disposed within a semiconductor layer and a stress adjusting layer. The photosensitive region is sensitive to light incident on a backside of the BSI CMOS image sensor to collect an image charge. The stress adjusting layer is disposed on a backside of the semiconductor layer to establish a stress characteristic that encourages photo-generated charge carriers to migrate towards the photosensitive region.
    Type: Grant
    Filed: August 10, 2010
    Date of Patent: December 25, 2012
    Assignee: OmniVision Technologies, Inc.
    Inventors: Hsin-Chih Tai, Howard E. Rhodes, Wei Zheng, Vincent Venezia, Yin Qian, Duli Mao
  • Patent number: 8330199
    Abstract: To eliminate the substrate voltage dependences of the respective resistance values of resistor elements, in the resistor elements coupled in series to each other over respective substrate regions, the ends of the resistor elements are coupled to the corresponding substrate regions by respective bias wires such that respective average potentials between the substrate regions of the resistor elements and the corresponding resistor elements have opposite polarities, and equal magnitudes.
    Type: Grant
    Filed: September 30, 2009
    Date of Patent: December 11, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Masaomi Kamakura, Toshio Kumamoto, Takashi Okuda
  • Patent number: 8330160
    Abstract: The objective is to provide a random number generating device having a smaller circuit size and a smaller value of output bias. The random number generating device includes a pair of first and second current paths arranged in parallel with each other, and a pair of first and second fine particles, which can mutually exchange charges, and are located in the vicinity of the first and second current paths.
    Type: Grant
    Filed: June 20, 2008
    Date of Patent: December 11, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsufumi Tanamoto, Shinobu Fujita
  • Patent number: 8324053
    Abstract: This invention discloses a method for manufacturing a semiconductor power device in a semiconductor substrate comprises an active cell area and a termination area.
    Type: Grant
    Filed: September 30, 2009
    Date of Patent: December 4, 2012
    Assignee: Alpha and Omega Semiconductor, Inc.
    Inventors: Madhur Bobde, Lingpeng Guan, Anup Bhalla
  • Patent number: 8325939
    Abstract: This specification describes technologies relating to editing audio data. In general, one aspect of the subject matter described in this specification can be embodied in methods that include receiving an audio signal including digital audio data; receiving an input identifying particular audio data of the audio signal corresponding to a noise pulse; and replacing the audio data corresponding to the detected noise pulse using interpolation of adjacent audio data to generate an edited audio signal. Other embodiments of this aspect include corresponding systems, apparatus, and computer program products.
    Type: Grant
    Filed: September 19, 2008
    Date of Patent: December 4, 2012
    Assignee: Adobe Systems Incorporated
    Inventors: Brian King, Charles Van Winkle
  • Patent number: 8324673
    Abstract: Semiconductor memory devices and methods of forming the same are provided, the semiconductor memory devices include a first and a second buried gate respectively disposed on both inner sidewalls of a groove formed in an active portion and a device isolation pattern. The first and second buried gates are controlled independently from each other.
    Type: Grant
    Filed: November 1, 2010
    Date of Patent: December 4, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Woo Chung, Kang-Uk Kim, Yongchul Oh, Hui-Jung Kim, Hyun-Gi Kim
  • Patent number: 8319210
    Abstract: A light-emitting element disclosed in the present invention includes a light-emitting layer and a first layer between a first electrode and a second electrode, in which the first layer is provided between the light-emitting layer and the first electrode. The present invention is characterized by the device structure in which the first layer comprising a hole-transporting material is doped with a hole-blocking material or an organic compound having a large dipole moment. This structure allows the formation of a high performance light-emitting element with high luminous efficiency and long lifetime. The device structure of the present invention facilitates the control of the rate of the carrier transport, and thus, leads to the formation of a light-emitting element with a well-controlled carrier balance, which contributes to the excellent characteristics of the light-emitting element of the present invention.
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: November 27, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoko Shitagaki, Satoshi Seo, Ryoji Nomura
  • Patent number: 8319253
    Abstract: The device including an active layer composed of AlGaInP, and an n-type clad layer and a p-type clad layer disposed so as to sandwich the active layer, the n-type clad layer and the p-type clad layer each having a bandgap greater than the bandgap of the active layer. The n-type clad layer includes a first n-type clad layer composed of AlGaInP and a second n-type clad layer composed of AlInP; and the second n-type clad layer has a thickness in the range from 40 nm to 200 nm.
    Type: Grant
    Filed: January 19, 2011
    Date of Patent: November 27, 2012
    Assignee: Stanley Electric Co., Ltd.
    Inventors: Wataru Tamura, Chiharu Sasaki
  • Patent number: 8319254
    Abstract: A micro-electromechanical system (MEMS) device includes a substrate, a first beam, a second beam, and a third beam. The first beam includes first and second portions separated by an isolation joint. The first and second portions each comprise a semiconductor and a first dielectric layer. An electrically conductive trace is mechanically coupled to the first beam and electrically coupled to the second portion's semiconductor but not the first portion's semiconductor. The second beam includes a second dielectric layer. The profile of each of the first second, and third beams has been formed by a dry etch. A cavity separates a surface of the substrate from the first, second, and third beams. The cavity has been formed by a dry etch. A side wall of each of the first, second, and third beams has substantially no dielectric layer disposed thereon, and the dielectric layer has been removed by a vapor-phase etch.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: November 27, 2012
    Assignee: Kionix, Inc.
    Inventors: Scott G. Adams, Andrew J. Minnick, Charles W. Blackmer, Mollie K. Devoe
  • Patent number: 8320582
    Abstract: An interference signal removing apparatus of a radio frequency (RF) receiver includes a low noise amplification unit which performs low noise amplification, a feedback processing unit which removes a necessary signal in a desired band from a signal output from the low noise amplification unit, and performs feedback of the signal from which the necessary signal is removed, and a signal processing unit which transmits a processed RF signal by synthesizing an input RF signal and the feedback signal to the noise amplification unit.
    Type: Grant
    Filed: May 19, 2008
    Date of Patent: November 27, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ick-jin Kwon, Jae-sup Lee, Han-woong Yoo
  • Patent number: 8309878
    Abstract: A universal power supply for use in a plasma arc system is disclosed. The power supply can include a plurality of power modules for providing a DC output from an AC input. Each of the power modules can include a rectifier, a converter, an inverter, an isolation transformer and an output rectifier. The power modules can include a power module controller configured to control at least one of the rectifier, the converter, or the inverter such that a DC output can be obtained from a wide variety of AC inputs. The power modules can be connected in parallel to provide a wide range of DC output currents for the power supply. The universal power supply can include a master controller coupled to each of the individual power module controllers to regulate the DC output current of the power supply by controlling the individual power module controllers.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: November 13, 2012
    Assignee: ITT Manufacturing Enterprises, Inc.
    Inventor: Jackie Winn
  • Patent number: 8311237
    Abstract: A howling suppression apparatus suppresses a howling caused in an acoustic system including a sound collection device and a sound emission device. An estimation part generates an estimated signal by estimating a feedback sound reaching the sound collection device from the sound emission device. An adjustment part generates an estimated signal by adjusting the estimated signal. A spectrum subtraction part generates an acoustic signal using a result of subtracting a frequency spectrum of the estimated signal from a frequency spectrum of an acoustic signal. A filter part generates an acoustic signal by suppressing a component of a frequency band including a howling frequency F among the acoustic signal. An acoustic signal in which the acoustic signal is amplified by an amplifier is supplied to the sound emission device.
    Type: Grant
    Filed: January 28, 2009
    Date of Patent: November 13, 2012
    Assignee: Yamaha Corporation
    Inventors: Hirobumi Tanaka, Hiraku Okumura
  • Patent number: 8304900
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; attaching an integrated circuit device to the substrate; forming a stud interconnect having stacked studs, the stud interconnect on the substrate and having a contact surface and a crown surface on an end of the stud interconnect opposite the substrate; applying an encapsulation over the integrated circuit die, over the stud interconnect, and over the substrate; and forming a cavity in the encapsulation over the stud interconnect, the contact surface and the crown surface exposed in the cavity.
    Type: Grant
    Filed: August 11, 2010
    Date of Patent: November 6, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Ki Youn Jang, YoungJoon Kim, JoHyun Bae
  • Patent number: 8304867
    Abstract: An integrated circuit (IC) device includes a substrate having a top surface including active circuitry including a plurality of I/O nodes, and a plurality of die pads coupled to the plurality of I/O nodes. A first dielectric layer including first dielectric vias is over the plurality of die pads. A redirect layer (RDL) including a plurality of RDL capture pads is coupled to the plurality of die pads over the first dielectric vias. A second dielectric layer including second dielectric vias is over the plurality of RDL capture pads. At least one of the second dielectric vias is a crack arrest via that has a via shape that includes an apex that faces away from a neutral stress point of the IC die and is oriented along a line from the neutral stress point to the crack arrest via to face in a range of ±30 degrees from the line. Under bump metallization (UBM) pads are coupled to the plurality of RDL capture pads over the second dielectric vias, and metal bonding connectors are on the UBM pads.
    Type: Grant
    Filed: November 1, 2010
    Date of Patent: November 6, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Robert Fabian McCarthy, Stanley Craig Beddingfield
  • Patent number: 8304804
    Abstract: An object of the present invention is to increase the light emission efficiency of a ZnO-based optical semiconductor device. An optical semiconductor device B has a structure which includes n-type Zn1-zMgzO (barrier layer) 11/Zn1-zMgxO (active layer) 15/p-type Zn1-yMgyO (barrier layer) 17, and light is emitted from the active layer 15. Electrodes 23, 21 are respectively formed on barrier layers 11, 17. By applying a voltage between the two electrodes 23, 21, light is emitted from ZnO (active layer) 15. Here, there are a relationship of x<y and a relationship of x<z. For instance, such values as x=0.1, y=0.15 and z=0.16 can be chosen. Otherwise, such values as x=0.15, y=0.25 and z=0.24 can be choose as well. In this case, by increasing the value x of the active layer, it is possible to shift its light emission wavelength to the shorter wavelength side. In addition, as shown in the above-described results, by increasing the value x, it is possible to enhance its light emission efficiency.
    Type: Grant
    Filed: May 13, 2008
    Date of Patent: November 6, 2012
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Hajime Shibata, Hitoshi Tampo, Koji Matsubara, Akimasa Yamada, Keiichiro Sakurai, Shogo Ishizuka, Shigeru Niki
  • Patent number: 8304995
    Abstract: A lamp includes a bracket having a cover, a lamp body fixed to the bracket by a shaft, a heating device and a pressure switch. The lamp body includes first and second portions at opposite sides of the shaft. The heating device is mounted at the first portion of the lamp body and the cover. The pressure switch is mounted to the cover and engages with a top of the second portion. When a weight of the snow/ice accumulated on the first portion of the lamp body is beyond a set value, the pressure switch controls the heating device to be switched on to melt the snow/ice; when the weight of the snow/ice accumulated on the lamp body decreases to be less than the set value, the pressure switch controls the heating device to be switched off.
    Type: Grant
    Filed: April 30, 2010
    Date of Patent: November 6, 2012
    Assignees: Fu Zhun Precision Industry (Shen Zhen) Co., Ltd., Foxconn Technology Co., Ltd.
    Inventors: Chin-Long Ku, Chin-Wen Yeh, Zhen-Neng Lin
  • Patent number: 8288781
    Abstract: Disclosed are a light emitting device and a method of fabricating the same. The light emitting device comprises a substrate. A plurality of light emitting cells are disposed on top of the substrate to be spaced apart from one another. Each of the light emitting cells comprises a first upper semiconductor layer, an active layer, and a second lower semiconductor layer. Reflective metal layers are positioned between the substrate and the light emitting cells. The reflective metal layers are prevented from being exposed to the outside.
    Type: Grant
    Filed: September 30, 2009
    Date of Patent: October 16, 2012
    Assignee: Seoul Opto Device Co., Ltd.
    Inventors: Won Cheol Seo, Joon Hee Lee, Jong Kyun You, Chang Youn Kim, Jin Cheul Shin, Hwa Mok Kim, Jang Woo Lee, Yeo Jin Yoon, Jong Kyu Kim
  • Patent number: 8288212
    Abstract: A method of fabricating a pixel structure of a thin film transistor liquid crystal display is provided. A transparent conductive layer and a first metallic layer are sequentially formed over a substrate. The first metallic layer and the transparent conductive layer are patterned to form a gate pattern and a pixel electrode pattern. A gate insulating layer and a semiconductor layer are sequentially formed over the substrate. A patterning process is performed to remove the first metallic layer in the pixel electrode pattern while remaining the gate insulating layer and the semiconductor layer over the gate pattern. A second metallic layer is formed over the substrate. The second metallic layer is patterned to form a source/drain pattern over the semiconductor layer. A passivation layer is formed over the substrate and then the passivation layer is patterned to expose the transparent conductive layer in the pixel electrode pattern.
    Type: Grant
    Filed: March 15, 2011
    Date of Patent: October 16, 2012
    Assignee: Au Optronics Corporation
    Inventors: Mao-Tsun Huang, Tzufong Huang
  • Patent number: 8283788
    Abstract: Method of fabricating thin-film transistors in which contact with connecting electrodes becomes reliable. When contact holes are formed, the bottom insulating layer is subjected to a wet etching process, thus producing undercuttings inside the contact holes. In order to remove the undercuttings, a light etching process is carried out to widen the contact holes. Thus, tapering section are obtained, and the covering of connection wiring is improved.
    Type: Grant
    Filed: September 16, 2010
    Date of Patent: October 9, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hongyong Zhang
  • Patent number: 8283754
    Abstract: A method includes providing a substrate having a seal ring region and a circuit region, forming a seal ring structure over the seal ring region, forming a first frontside passivation layer above the seal ring structure, etching a frontside aperture in the first frontside passivation layer adjacent to an exterior portion of the seal ring structure, forming a frontside metal pad in the frontside aperture to couple the frontside metal pad to the exterior portion of the seal ring structure, forming a first backside passivation layer below the seal ring structure, etching a backside aperture in the first backside passivation layer adjacent to the exterior portion of the seal ring structure, and forming a backside metal pad in the backside aperture to couple the backside metal pad to the exterior portion of the seal ring structure. Semiconductor devices fabricated by such a method are also provided.
    Type: Grant
    Filed: November 1, 2010
    Date of Patent: October 9, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jeng-Shyan Lin, Dun-Nian Yaung, Jen-Cheng Liu, Hsin-Hui Lee, Wen-De Wang, Shu-Ting Tsai