Abstract: A data bus reservation system controls data transfer between storage control elements (SCEs) in a multi-processor system. Each SCE is assigned a default bidirectional (BIDI) data bus for transfer of data. If a request for data transfer is made and the default data bus is already reserved, then the requestor must wait for the data bus to become available and a token passed to the requestor. When the token is passed to the requester, it has priority to reserve an available data bus. The token is passed to a different processor with each machine cycle. Additionally, there is error checking logic which checks a confirmation sent to the other SCE when the BIDI bus has been reserved.

Abstract: A system for querying disparate, heterogeneous data sources over a network includes a request translator and a data translator. The request translator translates a request having an associated data context declared by the requester into a query having a second data context associated with it. The second context is also associated with, and is declared by, at least one of the disparate data sources. This system also includes a data translator, which translates received data from the data context declared by the data source queried into the data context associated with the request.

Abstract: A method and apparatus for reducing the number of programmable architecture elements required for implementing a look-up table in a programmable logic device. At least one logic function to be performed by the look-up table is chosen. An output state is determined for each set of inputs to the look-up table, the output state being an array of outputs of the look-up table. Each output state is made up of responses of the chosen logic functions to a particular set of input variables. Identical output states are formed into groups. Selected groups of the output states which do not require programmable architecture elements are eliminated. A programmable architecture element is then assigned for each remaining group of output states.

Abstract: An improved client-server architecture of the present invention utilizes the advantages of known QOS networks to provide guaranteed quality of service, security, and a charge mechanism for handling requests initiated over a packet network, such as the Internet, for access to distributed media sources. Such media sources may be independent of the QOS network provider and may be located by browsing the Internet. A method of operating a client-server network enables the system level merger of the Internet and a guaranteed QOS network, such as the public switched telephone network, in order to provide the users with a complete information superhighway today. It will appear to the average user that the Internet and the QOS network are fused together.

Abstract: In accordance with the present invention, an FPGA input/output buffer including at least two registers is provided. A first register provides the FPGA output through a tristate buffer to the pad or pin. A second register controls the state of the tristate buffer. By placing an address on address lines controlling the register clocks, any selected one of the input/output buffers can be accessed. In one embodiment, separate addresses are provided for loading a tristate control value into the second register and for loading data into the first register.

Abstract: A firewall isolates computer and network resources inside the firewall from networks, computers and computer applications outside the firewall. Typically, the inside resources could be privately owned databases and local area networks (LAN's), and outside objects could include individuals and computer applications operating through public communication networks such as the Internet. Usually, a firewall allows for an inside user or object to originate connection to an outside object or network, but does not allow for connections to be generated in the reverse direction; i.e. from outside in. The disclosed invention provides a special "tunneling" mechanism, operating on both sides of a firewall, for establishing such "outside in" connections when they are requested by certain "trusted" individuals or objects or applications outside the firewall.

Abstract: A method in a computer system which includes receiving a first instruction which indicates indicates termination of execution of instructions which operate upon packed data stored in a first storage area. The first storage area is used for modifying data responsive to execution of floating point instructions. A plurality of tags is associated with the first storage area indicating that locations in the first storage area are either empty or non-empty responsive to the execution of the floating point instructions which modify data contained in the first storage area. Responsive to the receiving of the first instruction which indicates termination of execution of instructions which operate upon the packed data stored in the first storage area, the method sets only the plurality of tags to an empty state. In different embodiments, setting of the plurality of tags to a non-empty state occurs responsive to receiving a second instruction.

Abstract: A message unit that provides a hardware queue interface between a host processor and a local processor handling I/O operations in an I/O platform. Circuitry manages the head and tail pointers of an inbound free queue, an inbound post queue, an outbound free queue and an outbound post queue. Circuitry is also provided for enabling a host processor or bus agent to access these queues in a single bus transaction by reading or writing inbound port registers or outbound port registers. The queue elements contain handles of message buffers. The invention automatically performs the specific task of locating the next element in a queue, altering that element, and modifying a queue descriptor (i.e., a head or a tail pointer) to indicate the next element for a next queue access. A plurality of registers are used for selectively interrupting either the host processor or the local processor when the queues are written to by either the host processor, a bus agent, or the local processor.

Abstract: An integrated processor is fabricated on a single monolithic circuit and employs circuitry to accommodate data-intensive, view-intensive and voice-intensive requirements of modern-day PIDs. The integrated processor includes a CPU core, a memory controller, and a variety of peripheral devices to achieve versatility and high performance functionality. The integrated processor consumes less power by provision of a clock control unit including a plurality of phase-locked loops for generating clock signals of differing frequencies to appropriately clock the various subsystems of the integrated processor. The clock signals provided to the various subsystems by the clock control unit are derived from a single crystal oscillator input signal. A power management unit is incorporated within the integrated processor to control the frequency and/or application of certain clock signals to the various subsystems, as well as to control other power management related functions.

Abstract: A system for interconnecting line cards attached to a networking hub is disclosed. The disclosed system operates by forming backplane networks between the line cards using shared data path resources within the hub. Each line card attached with the hub describes its hub internal networking characteristics and capabilities. A hub management agent obtains the specific capabilities and characteristics of each line card attached to the networking hub, from each of the line cards. The characteristics and capabilities of each line card include which of the shared data path resources are accessible to the line card, and how the line card is able to operate on those accessible shared data path resources. The capabilities and characteristics of the line cards are obtained by the management agent requesting each line card for the information. The request is initiated by a triggering event, for example power-up of the networking hub or attachment of a new line card to the networking hub.

Abstract: An asynchronous switching apparatus is enabled to reshape data pulses and eliminate skewing problems as data is transmitted through the switch. The switching apparatus still functions asynchronously and maintains all the advantages of asynchronous operation, such as, not requiring the alignment and distribution of a central clock, having no central point failure mechanisms, and allowing each node of the parallel system to function free of synchronization requirements with other nodes.

Abstract: An output control apparatus is interposed between a host computer for generating data and a printer, and controls the printer. The control apparatus includes a plurality of data generators, a discriminator, a controller and a notifying device. The data generators interpret a plurality of printer languages and perform control processing. The discriminator analyzes received data and specifies by which of the plurality of data generators control based upon the received data is to be carried out. The controller, in a case where one data generator is not specified by the discriminator and an error resulting from interpretation failure occurs during the course of processing by one data generator selected under prescribed conditions, causes the discriminator to re-execute processing based upon data in which the interpretation failure occurred. The notifying device notifies of a request for re-transmission of data in a case where one of the data generators is specified anew by the controller.

Abstract: Methods and apparatus are provided for selecting advertisements and other information from a computer network database based on user defined preferences and transmitting the selected advertisement in background mode over a communications link between the computer network and a local computer with minimal interference with other processes communicating over the communications link. This method includes monitoring the communications link and transmitting portions of the advertisement when the communications link line utilization is below a preestablished threshold. Methods and apparatus are also provided for displaying or otherwise presenting the selected advertisements on the user's computer. Additional methods and apparatus are provided for selecting and presenting information stored on a local storage media based on user defined preferences.

Abstract: An apparatus and method for temporarily slaving and configuring a plurality of hardware resources such as computers, microprocessor-based devices, and the like, over a network, and then emancipating the resources to operate independently. Resources or targets may be enslaved at an operating system level. A controller may configure a plurality of hardware resources such as computers, microprocessor-based devices, and the like, to operate autonomously over a network. Resources or targets may be enslaved at an operating system level, configured with commands from a controller, and emancipated to operate independently. Emancipated resources may download applications, read and write files, communicate with other devices, and otherwise operate as independent computers. Data corresponding to test instructions may be downloaded from, and data corresponding to results may be recorded and saved on, a network server by a resource operating independently.

Abstract: A pipeline structure processes data in a series of stages, each of which has a data input latch (LDIN) and passes it on to the next stage in the pipeline via a data output latch (LDOUT). The stages are preferably connected to two non-overlapping clock phases (PH0, PH1). Adjacent stages are also connected via a validation line (IN.sub.-- VALID, OUT.sub.-- VALID) and an acceptance line (IN.sub.-- ACCEPT, OUT.sub.-- ACCEPT), and in some embodiments also via an extension bit line (IN.sub.-- EXTN, OUT.sub.-- EXTN). Input data is transferred from any stage to the following device on every complete period of both clock signals only if both the validation and acceptance signals in the respective latch are in an affirmative state, whereby data is transferred between stages regardless of the state of the validation and acceptance signals in other stages. A two-wire interface is thus formed between the stages.

Abstract: The programmable state machine includes a tag entry array and a new state array. All permissible combinations of current states and input values are represented within the tag entry array. The corresponding new state, to be transitioned to for each combination of current states and input values, is stored in the new state array. The tag entry array receives the current state and the input signals and generates a hit signal identifying which of the tag entries corresponds to the current state and input value signals. The new state array outputs the corresponding new state, based upon the hit signal received. In one embodiment, the tag entry array is configured as a fully associative cache tag entry array. In another embodiment, the tag entry array is configured as a set associative cache array. To eliminate the need to redundantly store a single new state, that corresponds to a large number of different transitions, a compare under mask arrangement is provided.

Abstract: An apparatus and method of efficiently and dynamically generating the addresses associated with a set of instructions in a microprocessor pipeline is disclosed. Program counter age bits associated with the offsets of an address of a predetermined instruction within a set of instructions are used to indicate the chronological age of each instruction within the set of instructions. The age bits are generated by a logic circuit which also dispatches instructions to various execution units. The age bits are used to maintain and track the addresses of an instruction stream within a processing system so that there is no need to store the addresses of each and every instruction.

Abstract: A microprocessor including a pair of caches is provided. One of the pair of caches is accessed by stack-relative memory accesses from the decode stage of the instruction processing pipeline. The second of the pair of caches is accessed by memory accesses from the execute stage of the instruction processing pipeline. When a miss is detected in the first of the pair of caches, the stack-relative memory access which misses is conveyed to the execute stage of the instruction processing pipeline. When the stack-relative memory access accesses the second of the pair of caches, the cache line containing the access is transmitted to the first of the pair of caches for storage. The first of the pair of caches selects a victim line for replacement when the data is transferred from the second of the pair of caches. If the victim line has been modified while stored in the first cache, then the victim line is stored in a copyback buffer.

Abstract: A data processing system includes a CPU, an address decoder for generating a location designation signal which designates a location of a predetermined area of address area meeting a predetermined correspondence relation to a numerical address supplied from the CPU, and a memory securing locations of a plurality of areas capable of being designated by the location designation signal for the address decoder.

Abstract: In order to reduce the size of the memory employed to store firmware, the firmware is written in virtual control words which are then reduced by allotting them to a primary control word memory and at least one secondary control word memory which is addressed by a field in the primary control word memory. A virtual set of secondary control words are each divided into a plurality of fields, and each field of each secondary virtual control word is marked as guarded or "don't care". If a field is marked as "don't care", the function represented by the virtual control word will perform properly no matter what the content of that field. Virtual control word pairs are then examined to ascertain if they can be combined into a single control word.