Abstract: A method and network interface logic for providing an embedded checksum in a packet transferred over a packet network. The packet network comprises a plurality of interconnected, directly-attached computers operative to provide data fidelity between any neighboring pair of such computers at least as robust as such data fidelity between any non-neighboring pair of such computers. Each computer comprises packet storage means and network interface means. Such a packet is sent directly onto the packet network from the packet storage means of a source computer using its network interface means. The packet is received from the packet network and transferred directly into the packet storage means of a sibling computer using its network interface means. Such an embedded checksum is associated with the packet at the sibling computer with the embedded checksum being calculated by at least one of the source computer or the sibling computer based on substantially the entire packet for validating error-free receipt.

Abstract: In an information processor formed of a program storage unit 2, a data pair production unit 3 and an operation unit 4 including an accumulator 41, when the sum of products of data ai and bi of the same generation .SIGMA. (ai*bi) is produced, a cumulative products instruction code MULA is read out from program storage unit 2. When a data pair related to the instruction code MULA is detected in production portion 3, a multiplication processing of the data pair and accumulation a processing of the multiplication result values using accumulator 41 according to the instruction code MULA are continuously executed in operation unit 4. Accordingly, the order of executing operation processing according to the instruction code MULA including the above-described multiplication processing and accumulation processing is not limited by the order of generations, and therefore data of different generations can be processed in parallel.

Abstract: In a first aspect of the invention, branch prediction hardware, comprising logic and interconnect, is configurable via a control line to alter the manner in which the branch prediction is generated. The configuration can be done programmatically in software. Or, the configuration can be done by hardware in response to processor events. Such processor events include the loading of the CS register and changes in the instruction workload. In a second aspect of the invention, related to speculative execution, the directions of a plurality of branches are predicted based partly on resolved branch history information. Tentative branch history information is then stored for each of the predicted branches. When a predicted branch is resolved, the resolved branch history information is updated based on the stored tentative branch history information for the branch most recently resolved. Additionally, the predictions may be partly based on preceding unresolved branch predictions if any are outstanding.

Abstract: A new programmable logic device architecture with an improved LAB and improved interconnection resources. For interconnecting signals to and from the LABs (200), the global interconnection resources include switch boxes (310), long lines (340 and 350), double lines (360 and 370), single lines (385), and half- (330) and partially populated (320) multiplexer regions. The LAB includes two levels of function blocks. In a first level, there are eight four-input function blocks (601). In a second level, there are two four-input function blocks (670) and four secondary two-input function blocks (672). In one embodiment, these function blocks are implemented using look-up tables (LUTs). The LAB has combinatorial and registered outputs. The LAB also contains storage blocks (691) for implementing sequential or registered logic functions. The LAB has a carry chain for implementing logic functions requiring carry bits. The LAB may also be configured to implement a random access memory.

Abstract: A method for providing rapid recovery from a network file server failure through the use of a backup computer system. The backup computer system runs a special mass storage access program that communicates with a mass storage emulator program on the network file server, making the disks (or other mass storage devices) on the backup computer system appear like they were disks on the file server computer. By mirroring data by writing to both the mass storage of the file server and through the mass storage emulator and mass storage access program to the disks on the backup computer, a copy of the data on the file server computer is made. Optionally, selected portions of the data read through the mass storage emulator program can be altered before being returned as the result of the read operation on the file server. In the event of failure of the file server computer, the backup computer can replace the file server, using the copy of the file server's data stored on its disks.

Abstract: An integrated circuit comprises a microprocessor (1), a memory (2) and one or more internal peripherals (3) connected, firstly, to one another and, secondly, to circuits external (4) to this integrated circuit by means of connections circuits (5). The peripherals comprise circuits called options circuits (6) enabling the operation of these peripherals to be configured. For an operating session corresponding to putting of the integrated circuit into service, the operations of these peripherals are defined as a function of information elements stored in the the first part of the memory (7). The memory also has a second part (8) designed to store instructions that can be executed by the microcontroller. This configuration of the peripherals takes place when the integrated circuit is put into service, by the linking of said peripherals to said first part of the memory. This memory is of the programmable type.

Abstract: A multi-standard video decompression apparatus has a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system.

Abstract: A system for interconnecting line cards attached to a networking hub is disclosed. The disclosed system operates by forming backplane networks between the line cards using shared data path resources within the hub. Each line card attached with the hub describes its hub internal networking characteristics and capabilities. A hub management agent obtains the specific capabilities and characteristics of each line card attached to the networking hub, from each of the line cards. The characteristics and capabilities of each line card include which of the shared data path resources are accessible to the line card, and how the line card is able to operate on those accessible shared data path resources. The capabilities and characteristics of the line cards are obtained by the management agent requesting each line card for the information. The request is initiated by a triggering event, for example power-up of the networking hub or attachment of a new line card to the networking hub.

Abstract: A conventional SIMD processor array architecture's functions are amplified by a SIMIMD architecture where more programmable flexibility would be useful. Decision making in general and specifically classification where decision trees are common, is a problem eased by SIMIMD. A SIMD array processor having a plurality of pickets in SIMIMD mode allows each picket to occasionally execute data-dependent instructions that are different from the instructions in other pickets to greatly improve execution efficiency in decision making areas. Every element in A SIMD array of processors receives a stream of commands from the array controller. Here several mechanisms allow an array machine with individual processing elements, called pickets, to interpret some of the SIMD commands in their own unique way, giving each picket a degree of local autonomy. A resulting capability allows the pickets to execute instructions in a mode called SIMIMD.

Abstract: A method of configuring a network. The network includes some physical devices, some hosts, and a network management tool. The method comprises the following steps. First, generate a set of leaf nodes. Each leaf node includes at least one physical device and connects to at least one host. Next, generate an adjacency matrix from said set of leaf nodes. Next, generate a set of interconnect nodes, the interconnect nodes connect the set of leaf nodes. Next, determine the resource availability for the set of interconnect nodes. Finally, configure the set of interconnect nodes and the set of leaf nodes after determining that sufficient resources are available.

Abstract: A router includes a routing table containing flags each representing a public-network side or a LAN side. A path for a received packet is determined such that the packet is forwarded to the next node through the LAN according to the next node address when the flag corresponding to the specified destination represents the LAN side, and the packet is forwarded to the next node through the public network according to the next node address when the flag represents the public network side. When a change of the routing information sets is monitored, the routing table is searched for the second router having the flag representing the public network side and then the changed routing information sets are transmitted to the second router.

Abstract: A network element included in a telecommunication system contains several nodes (1226, 1232, 1234, 1236, 1238) which are included in a system internal to this network element and provides internal network element functions in an internal bearer service network, and internal resources in the form of hardware and software which are used for performing the internal network element functions.The network element can offer an operations system a "white box" view, implying that internal resources are available to this operations system, enabling it to use managed objects representing the internal resources in order to manage the resources according to a second management information model in connection with using them for performing internal network element functions.

Abstract: A multi-level identification apparatus and method for providing at least two types of identification information, including a first type for identifying the origin of a microprocessor and the number of levels of identification information available, and a second type for identifying a family, a model, a stepping ID, and features of a microprocessor. The apparatus includes a first memory element for storing an indicia string that identifies the origin of the microprocessor. The apparatus also includes a second memory element for storing other microprocessor ID data including data fields for specifically identifying the microprocessor. The apparatus includes control logic for executing an ID instruction that reads the indicia string or the microprocessor ID data, dependent upon a preselected type. Whichever identification information is read, it is stored in one or more general purpose registers for selective reading by a programmer. The method is available at any time while the microprocessor is operating.

Abstract: Systems are provided for saving register data in a pipelined data processing system, and for restoring the data to the appropriate register in the event of an exception condition. One embodiment concerns a latch feedback assembly, such as a SRL, which includes multiple series-connected latches having a feedback connection between last and first latches. The latches are clocked to temporarily reserve a delayed backup copy of data from the first latch on the last latch. Upon detection of an exception, the backup copy is first preserved by disabling writes to the last latch; then the backup copy is copied to the first latch to restore the first latch to its state prior to occurrence of the exception. Another embodiment involves a register file save/restore mechanism, in which an additional bank of registers, called a "backup register", is coupled to a register file. When data is stored in an address of the register file, the address and its data content are also stored in the backup register.

Abstract: A system and method is provide for managing input/output (I/O) resources in a computer system. The system includes a hardware resource manager which tracks the use of the I/O resources. In addition, the hardware resource manager can allocate the resources between device drivers and provide a standard implementation to be used by device drivers.

Abstract: A system and method are described which take an arbitrarily assembled collection of nodes on a bus or network and imposes an optimized hierarchical tree structure where there is only one root node. Nodes having both parent and child nodes are considered branch nodes while nodes having only parent nodes are leaf nodes. Loops or cycles in the physical topology are resolved into a logical topology that is acyclic and directed. A signaling scheme is developed in which nodes, via on board communications hardware, signal all connected nodes and respond accordingly until hierarchical relationships are established. Cycles are resolved by intelligently breaking links to yield an acyclic graph. Direction is established by each node recognizing its parent/child status with respect to connected nodes until a single node is established as a root node.

Abstract: An instruction for returning to a ROM is written to a position where data is not broken even if a next correction is executed in order not to the content of a register even if an interruption processing for correction and a processing for returning a ROM program are executed. A microcomputer connected through a serial i/O bus, an EEROM, and a correction data writing device comprises a CPU, a RAM, a ROM, a PC comparison register section, a ROM correction processing circuit having a PC value latch section, and a serial i/O section. The CPU sequentially executes an internal sequence control of the microcomputer and a logical operation in accordance with instructions written in the ROM as a program in advance. The RAM temporarily saves intermediate processing data of, e.g. calculation, or saves an adjustment value transferred from the EEPROM when the program is actually executed.

Abstract: A data processor that gives necessary and sufficient precision of analog-to-digital (A/D) conversion results according to the processing contents and the processing mode includes an A/D converter that digitizes an analog signal by repeatedly sampling and holding the signal at a frequency given by a clock signal, a coordinates processing part that obtains one piece of processing data by averaging n pieces of data output from the A/D converter, and a sampling-time/frequency control part that changes the number n and the sampling frequency to obtain a necessary precision of digital data.

Abstract: A parallel processor system controls access to a distributed shared memory and to plural cache memories to prevent frequently-used local data from being flushed out of a cache memory. The parallel processor system includes a plurality of nodes each including a processor and a shared memory in a distributed shared memory arrangement, and a local-remote divided cache memory system, wherein local data and remote data are controlled separately. Each local-remote divided cache memory system includes a local data area, a remote data area, and a cache memory controller by which either the local data area or the remote data area is accessed according to the contents of an access request.

Abstract: A generic network device includes a serial line switching apparatus for performing either parallel or serial communications amongst multiple nodes over switching networks. An aspect includes is the adaptation of standard and proprietary serial interfaces using either optical or electrical transmission media to interface to the parallel switch. The converted serial data is routed to the selected destination through the parallel switch network, where it is received and converted back into a serial optical or electrical interface/protocol. Thus, the combination of the switching adapter and an ALLNODE parallel switching network make it feasible for serial message data to be switched and routed to various destinations.