Abstract: A system and method for routing administrative data over a telecommunications network to a remote processor establishes a connection between a router and the remote processor over a primary link. A processor associated with the router is adapted to detect a predetermined condition and thereupon to automatically reconfigure the router to establish another connection with the remote processor or a connection with another remote processor. The data may be routed over a telecommunications switching network using a router having inverse multiplexing capability. Further, a sockets connection may be established between the associated processor and the remote processor for monitoring the status of the connection between the router and the remote processor to detect a predetermined condition such as a link failure. External customer data may be routed to the system for remote archival purposes.

Abstract: The present invention provides a program control system including plural programs, plural execution means each of which executes the corresponding program of the plural programs, a memory for storing the plural programs, plural program counters each of which generates an address for reading the corresponding one of the programs from the memory, and a selector for selecting an output of one of the program counters and providing the output to the memory. Each of the programs stored in the memory and executed by the corresponding one of the execution means is indicated by the address generated by the corresponding one of the program counters selected by the selector, and the memory sequentially stores instructions in each of the programs.

Abstract: A naming service maintains lists of names for receiving messages, with the names having a defined format portion for routing messages in the network. At least some names have additional routing information that is passed to another server or service for routing the messages externally, such as with remote e-mail or facsimile transmission.

Abstract: A data system architecture and interface circuits permit slow devices having limited signal capacities to launch and receive information from a central bus. Data is clocked onto the bus with a master circuit at the leading and trailing edges of the bus clock so that portions of a large multibit signal are launched without having to wait for the initiation of a next clock cycle. Accordingly, data portions are launched during both leading and trailing edges of the clock signal. In the case of a simple bus device not able to accommodate inclusion of a slave interface circuit, the received signal packet is provided in adapted form anticipating that only a second half portion of the signal packet will actually be registered as received.

Abstract: A disc storage apparatus includes a disc having at least one recording surface, a head associated with the recording surface for recording data on the recording surface during a data write operation, and for reproducing data from the recording surface during a data read operation, a disc control unit for receiving data and outputting parallel data during the data write operation, and for receiving parallel data and outputting data during the data read operation, and an encoder/decoder circuit for receiving the parallel data from the disc control unit and outputting data to the head to be recorded on the recording surface during the data write operation, and for receiving from the head data reproduced from the recording surface and outputting parallel data to the disc control unit during the data read operation.

Abstract: A coprocessor has a systolic array of processors each associated with a memory; an array data bus conveying input data to and output data from connections to the array; data buffers for the input and output data; an input and output data bus communicating with the data buffers and with a host processor; a control bus conveying successive operation codes to the array processors an instruction control store containing instructions providing operation codes for successive operations of the array processors, and a sequencer to select instructions from the control store. An intermediate data bus with a microprocessor and further random access memory communicating with that bus, carries input and output data for the array, input and output data for the microprocessor, and addresses for the memories associated with the processors of the array and for the sequencer.

Abstract: A data driven type information processor includes a control unit having a function of storing a data flow program and accessing it, and a function of producing an operand data pair, the control unit further including one memory shared by both functions. When a program is executed, program data per 1 accessing to the memory and operand data related to the program data are read out simultaneously and applied to an operation unit. Accordingly, a program memory and a memory for queuing operand data, which, were separately provided in a conventional technique, are combined into a single mechanism. Thereby, the number of stages of processing in program execution in the information processor is reduced and increase in program execution speed is permitted.

Abstract: An indexing system and method are provided for improving retrieval of data based on a query from a user from a database management system including a main computer and a memory coupled to the main computer for storing the data. The indexing system includes a parallel computer coupled to the main computer and a parallel disk array coupled to the parallel computer. The invention includes the steps of storing record based data in the memory of the database management system, storing a value based index of selected attributes related to the record based data on the parallel disk array, and determining whether the parallel computer can be used to execute a query to obtain at least a partial result to the query. If so, the query is sent to the parallel computer and the query is executed on the parallel computer to obtain at least a partial result.

Abstract: This is a programmable processing system which comprises: one or more computer networks each of the networks has at least one population of processor nodes; at least one population of storage nodes; and at least one switch to provide transfer of information between the processor nodes and the storage nodes. Each processor node has at least one processing module comprising spatial light modulators; processors; and at least one hologram. Other methods and devices are disclosed.

Abstract: An address of any desired instruction in a super-scalar processor is generated using address tracking logic. A sequential address register in the last stage of the processor's pipelines holds the address of the last or oldest instruction in the pipelines. This register is updated with a target address when a branch instruction is actually taken. A pipeline valid array contains valid bits for the instructions in the pipelines, and also contains the lengths of the instructions for complex instruction sets having instructions that vary in length. The address of the desired instruction is calculated as the sum of a base address and an adjustment value. The base address is the address of the last instruction which is stored in the sequential address register when there are no intervening taken branches between the desired instruction and the last instruction in the pipelines.

Abstract: A method and system for resolving or preventing bus address conflicts between interface cards of a personal computer involves using a register instead of a switch to allow a user to select an address based on programming. When a conflict occurs between addresses of two interface cards, one of the interface cards may be re-addressed by re-programming the card with no need for manually setting a switch.

Abstract: A programmable workstation for collaborative working in a network comprises a conventional operating system and network control layer for controlling physical routing of data between nodes. A collaborative application subsystem which interfaces with application programs is responsive to a predetermined call from a collaboration call manager to establish the call manager at the node to handle incoming events which are not specific to any application program instances at the node.

Abstract: A method and apparatus for monitoring the status of a computer network by displaying polygon-shaped objects (or "icons") to represent groups of devices connected to the network. In a preferred embodiment each device (or "node") on the network is assigned to one of a number of groups (or "clusters"), each cluster is represented as a polygon-shaped object on a computer system display, and the number of sides for each polygon is displayed according to the size of the group represented. The appearance of the sides of each polygon may also help indicate the size of the group. A base value may be varied to partly govern the shape and appearance of the polygon.

Abstract: A communication system enables a system controller to allocate to a first system endpoint (e.g., application processor) control over one or more components of a second system endpoint (e.g., terminal). In response to a valid control request signal received from the first endpoint identifying one or more components at the second endpoint over which control is requested, the controller sends an acknowledgment signal to the first endpoint indicating that control over the identified component(s) has been allocated to the first endpoint. In response to the acknowledgment signal, an endpoint interface enables the first endpoint to directly communicate with the second endpoint using a first endpoint originated control signal which simulates a controller originated control signal for controlling the identified components at the second endpoint.

Abstract: An arithmetic engine includes a first dual multiplier accumulator (MAC) for receiving input data and for producing first dual MAC output data. A second dual MAC is coupled in parallel to the first dual MAC. The second dual MAC receives the input data and produces second dual MAC output data. An adder array is coupled to both the first dual MAC and to the second dual MAC. The adder array receives the input data, the first dual MAC output data, and the second dual MAC output data and produces arithmetic engine output data. Each dual MAC comprises a multiplier cross point switch, multiplier registers, a register selector, and parallel multipliers. Each adder array comprises a cross point switch, adder registers, a register selector, adder, and condition code determiner.

Abstract: A distributed processing system capable of realizing efficient management of a multiplicity of objects in a large scale distributed processing comprises an objectification unit which makes it possible to handle an assembly of objects as one object and a message transfer unit by which a request for a processing to one object provided by objectification by the objectification unit is made to an optimal one of plural objects subjected to objectification.

Abstract: A program controlled processor comprises a scalar processing unit 101 for normal data (=scalar) operations and branch processing, a plurality of vector processing units 102 of identical structure, a vector distributor 103 for distributing input data as block vectors to vector memory 304 in each vector processing unit 102, a vector coupler 104 for coupling the block vectors stored in vector memory 404 in each vector processing unit 102 to provide output vectors, an instruction memory 105 for storing the operations of these circuit blocks as an operating program, a sequencer 106 for sequentially reading the instruction memory 105, and a decoder 107 for interpreting the read instructions and outputting a control signal to each circuit block. The scalar processing unit 101 comprises a scalar bus input enabling the scalar processing unit 101 to refer scalar registers in the vector processing units 102.

Abstract: Novel object-oriented client-server facility (CSF) and networking service facility (NSF) interfaces implement communication between application programs residing in client and server nodes of a distributed services network. The CSF interface includes remote procedure call (RPC) objects for invoking and responding to service requests at the nodes, and application programming interface (API) objects for transporting those requests between the nodes. However, the API objects only provide communication transports within a node. Accordingly, the API and RPC objects interact with dynamically-configurable protocol stacks within the NSF interfaces to complete the transport mechanism needed by an application program on the client node when accessing services on a remote server node.

Abstract: In a data processing system, an input output bus unit (IOBU) is connected to one end of an input output interface controller (IOIC) via an asynchronous bus. The other end of the IOIC is connected to a storage controller (SC) and an input output interface unit (IOIU) via a synchronous bus. The SC and IOIU are connected to a memory unit and an instruction processing unit. The asynchronous bus, which is comprised of three sub-buses and a control bus, conducts signals between the IOIC and an IOBU in an asynchronous "handshaking" manner. The synchronous bus, which is comprised of two sub-buses and a control bus, conducts signals between the IOIC and the SC/IOIU in an synchronous manner. The IOIC, interconnected between the synchronous bus and asynchronous bus, functions as a buffer between the faster synchronous bus and the slower asynchronous bus.

Abstract: A message packet transmitter for transmitting a packet of electronic data signals onto a communication network without interruption. A first-in, first-out electronic memory has a transmit state in which an electronic data signal stored therein is output. The electronic memory has an idle state in which electronic data signals stored therein are not output. A message packet-in-transit identification circuit generates a packet-in-transit signal after the electronic memory outputs the first electronic data signal in a message packet. A no-packet-in-transit signal is generated after the electronic memory outputs the last electronic data signal in the message packet. A state controller maintains the electronic memory in the transmit state when the electronic memory stores at least a portion of a message packet, when the state controller receives a packet-in-transit signal, and when the state controller receives an interrupt-pending signal.